Author: Kostya Kortchinsky Date: 2020-05-11T09:09:18-07:00 New Revision: 11d203a2bbb17f123bb4370277bf36250efd07ef
URL: https://github.com/llvm/llvm-project/commit/11d203a2bbb17f123bb4370277bf36250efd07ef DIFF: https://github.com/llvm/llvm-project/commit/11d203a2bbb17f123bb4370277bf36250efd07ef.diff LOG: Add vendor identity check for Hygon Dhyana processor in Scudo Summary: The Hygon Dhyana processor supports hardware CRC32. Related link: https://reviews.llvm.org/D78874 Result of "make check": Testing Time: 1364.04s Unsupported Tests: 317 Expected Passes : 36802 Expected Failures: 161 [100%] Built target check-llvm [100%] Built target check Reviewers: cryptoad Reviewed By: cryptoad Subscribers: craig.topper, cryptoad, cfe-commits, #sanitizers, llvm-commits Tags: #clang, #sanitizers, #llvm Differential Revision: https://reviews.llvm.org/D62368 Added: Modified: compiler-rt/lib/scudo/scudo_utils.cpp compiler-rt/lib/scudo/standalone/checksum.cpp Removed: ################################################################################ diff --git a/compiler-rt/lib/scudo/scudo_utils.cpp b/compiler-rt/lib/scudo/scudo_utils.cpp index 5e76a4a30f10..f31d68058acb 100644 --- a/compiler-rt/lib/scudo/scudo_utils.cpp +++ b/compiler-rt/lib/scudo/scudo_utils.cpp @@ -62,6 +62,14 @@ FORMAT(1, 2) void NORETURN dieWithMessage(const char *Format, ...) { # ifndef bit_SSE4_2 # define bit_SSE4_2 bit_SSE42 // clang and gcc have diff erent defines. # endif + +#ifndef signature_HYGON_ebx // They are not defined in gcc. +// HYGON: "HygonGenuine". +#define signature_HYGON_ebx 0x6f677948 +#define signature_HYGON_edx 0x6e65476e +#define signature_HYGON_ecx 0x656e6975 +#endif + bool hasHardwareCRC32() { u32 Eax, Ebx, Ecx, Edx; __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx); @@ -71,7 +79,10 @@ bool hasHardwareCRC32() { const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) && (Ecx == signature_AMD_ecx); - if (!IsIntel && !IsAMD) + const bool IsHygon = (Ebx == signature_HYGON_ebx) && + (Edx == signature_HYGON_edx) && + (Ecx == signature_HYGON_ecx); + if (!IsIntel && !IsAMD && !IsHygon) return false; __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx); return !!(Ecx & bit_SSE4_2); diff --git a/compiler-rt/lib/scudo/standalone/checksum.cpp b/compiler-rt/lib/scudo/standalone/checksum.cpp index 5de049a0931b..05d4ba54bfc8 100644 --- a/compiler-rt/lib/scudo/standalone/checksum.cpp +++ b/compiler-rt/lib/scudo/standalone/checksum.cpp @@ -31,6 +31,13 @@ Checksum HashAlgorithm = {Checksum::BSD}; #define bit_SSE4_2 bit_SSE42 // clang and gcc have diff erent defines. #endif +#ifndef signature_HYGON_ebx // They are not defined in gcc. +// HYGON: "HygonGenuine". +#define signature_HYGON_ebx 0x6f677948 +#define signature_HYGON_edx 0x6e65476e +#define signature_HYGON_ecx 0x656e6975 +#endif + bool hasHardwareCRC32() { u32 Eax, Ebx = 0, Ecx = 0, Edx = 0; __get_cpuid(0, &Eax, &Ebx, &Ecx, &Edx); @@ -39,7 +46,10 @@ bool hasHardwareCRC32() { (Ecx == signature_INTEL_ecx); const bool IsAMD = (Ebx == signature_AMD_ebx) && (Edx == signature_AMD_edx) && (Ecx == signature_AMD_ecx); - if (!IsIntel && !IsAMD) + const bool IsHygon = (Ebx == signature_HYGON_ebx) && + (Edx == signature_HYGON_edx) && + (Ecx == signature_HYGON_ecx); + if (!IsIntel && !IsAMD && !IsHygon) return false; __get_cpuid(1, &Eax, &Ebx, &Ecx, &Edx); return !!(Ecx & bit_SSE4_2); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
