Author: Craig Topper Date: 2020-02-10T14:14:40+01:00 New Revision: 8b8a4834a4b8aaff751c95e458d7a01ceae081a2
URL: https://github.com/llvm/llvm-project/commit/8b8a4834a4b8aaff751c95e458d7a01ceae081a2 DIFF: https://github.com/llvm/llvm-project/commit/8b8a4834a4b8aaff751c95e458d7a01ceae081a2.diff LOG: [X86] Use MVT::i8 instead of MVT::i64 for shift amount in BuildSDIVPow2 X86 uses i8 for shift amounts. This code can fail on a 32-bit target if it runs after type legalization. This code was copied from AArch64 and modified for X86, but the shift amount wasn't changed to the correct type for X86. Fixes PR44812 (cherry picked from commit ec9a94af4d5fb3270f2451fcbec5a3a99f4ac03a) Added: llvm/test/CodeGen/X86/pr44812.ll Modified: llvm/lib/Target/X86/X86ISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0f152968ddfd..cbdd7135de43 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -21056,7 +21056,7 @@ X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor, // Divide by pow2. SDValue SRA = - DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i64)); + DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i8)); // If we're dividing by a positive value, we're done. Otherwise, we must // negate the result. diff --git a/llvm/test/CodeGen/X86/pr44812.ll b/llvm/test/CodeGen/X86/pr44812.ll new file mode 100644 index 000000000000..7c4dc67dc9c0 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr44812.ll @@ -0,0 +1,24 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=cmov | FileCheck %s + +define <2 x i32> @foo(<2 x i32> %tmp) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax +; CHECK-NEXT: leal 7(%eax), %ecx +; CHECK-NEXT: testl %eax, %eax +; CHECK-NEXT: cmovnsl %eax, %ecx +; CHECK-NEXT: sarl $3, %ecx +; CHECK-NEXT: movl $1717986919, %eax # imm = 0x66666667 +; CHECK-NEXT: imull {{[0-9]+}}(%esp) +; CHECK-NEXT: movl %edx, %eax +; CHECK-NEXT: shrl $31, %eax +; CHECK-NEXT: sarl $2, %edx +; CHECK-NEXT: addl %edx, %eax +; CHECK-NEXT: movl %ecx, %edx +; CHECK-NEXT: retl +entry: + %tmp1 = sdiv <2 x i32> %tmp, <i32 10, i32 8> + ret <2 x i32> %tmp1 +} + _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
