Author: Austin Kerbow Date: 2019-11-07T16:29:43-08:00 New Revision: 64bc08ac4acc89628cdadc30764631723448ca0f
URL: https://github.com/llvm/llvm-project/commit/64bc08ac4acc89628cdadc30764631723448ca0f DIFF: https://github.com/llvm/llvm-project/commit/64bc08ac4acc89628cdadc30764631723448ca0f.diff LOG: Merging r375265: ------------------------------------------------------------------------ r375265 | kerbowa | 2019-10-18 11:20:30 -0700 (Fri, 18 Oct 2019) | 13 lines AMDGPU: Fix SMEM WAR hazard for gfx10 readlane Summary: Hazard recognizer fails to see hazard with V_READLANE_B32_gfx10. Reviewers: rampitec Reviewed By: rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69172 ------------------------------------------------------------------------ Added: Modified: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir Removed: ################################################################################ diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 885239e2faed..4e8773203afb 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -952,6 +952,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) { unsigned SDSTName; switch (MI->getOpcode()) { case AMDGPU::V_READLANE_B32: + case AMDGPU::V_READLANE_B32_gfx10: case AMDGPU::V_READFIRSTLANE_B32: SDSTName = AMDGPU::OpName::vdst; break; diff --git a/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir b/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir index 0796754ddf9c..531cca11e47b 100644 --- a/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir +++ b/llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir @@ -304,6 +304,21 @@ body: | S_ENDPGM 0 ... +# Workaround since spilling/restoring SGPRs use real opcodes. +# GCN-LABEL: name: hazard_smem_war_readlane_gfx10 +# GCN: S_LOAD_DWORD_IMM +# GCN: $sgpr_null = S_MOV_B32 0 +# GCN-NEXT: V_READLANE_B32_gfx10 +--- +name: hazard_smem_war_readlane_gfx10 +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0 + $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0 + $sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3 + S_ENDPGM 0 +... + # GCN-LABEL: name: hazard_smem_war_readfirstlane # GCN: S_LOAD_DWORD_IMM # GCN: $sgpr_null = S_MOV_B32 0 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
