Author: hans Date: Fri Aug 17 00:38:52 2018 New Revision: 339999 URL: http://llvm.org/viewvc/llvm-project?rev=339999&view=rev Log: Merging r339945: ------------------------------------------------------------------------ r339945 | ctopper | 2018-08-16 23:54:02 +0200 (Thu, 16 Aug 2018) | 9 lines
[X86] In EFLAGS copy pass, don't emit EXTRACT_SUBREG instructions since we're after peephole Normally the peephole pass converts EXTRACT_SUBREG to COPY instructions. But we're after peephole so we can't rely on it to clean these up. To fix this, the eflags pass now emits a COPY with a subreg input. I also noticed that in 32-bit mode we need to constrain the input to the copy to ensure the subreg is valid. Otherwise we'll fail verify-machineinstrs Differential Revision: https://reviews.llvm.org/D50656 ------------------------------------------------------------------------ Added: llvm/branches/release_70/test/CodeGen/X86/pr38539.ll - copied unchanged from r339945, llvm/trunk/test/CodeGen/X86/pr38539.ll Modified: llvm/branches/release_70/ (props changed) llvm/branches/release_70/lib/Target/X86/X86FlagsCopyLowering.cpp llvm/branches/release_70/test/CodeGen/X86/flags-copy-lowering.mir Propchange: llvm/branches/release_70/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Fri Aug 17 00:38:52 2018 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339769,339883 +/llvm/trunk:155241,338552,338554,338569,338599,338610,338658,338665,338682,338703,338709,338716,338751,338762,338817,338902,338915,338968,339073,339166,339179,339184,339190,339225,339316,339319,339411,339492,339515,339533,339535-339536,339600,339636,339769,339883,339945 Modified: llvm/branches/release_70/lib/Target/X86/X86FlagsCopyLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=339999&r1=339998&r2=339999&view=diff ============================================================================== --- llvm/branches/release_70/lib/Target/X86/X86FlagsCopyLowering.cpp (original) +++ llvm/branches/release_70/lib/Target/X86/X86FlagsCopyLowering.cpp Fri Aug 17 00:38:52 2018 @@ -97,6 +97,7 @@ public: private: MachineRegisterInfo *MRI; + const X86Subtarget *Subtarget; const X86InstrInfo *TII; const TargetRegisterInfo *TRI; const TargetRegisterClass *PromoteRC; @@ -346,10 +347,10 @@ bool X86FlagsCopyLoweringPass::runOnMach LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName() << " **********\n"); - auto &Subtarget = MF.getSubtarget<X86Subtarget>(); + Subtarget = &MF.getSubtarget<X86Subtarget>(); MRI = &MF.getRegInfo(); - TII = Subtarget.getInstrInfo(); - TRI = Subtarget.getRegisterInfo(); + TII = Subtarget->getInstrInfo(); + TRI = Subtarget->getRegisterInfo(); MDT = &getAnalysis<MachineDominatorTree>(); PromoteRC = &X86::GR8RegClass; @@ -960,10 +961,14 @@ void X86FlagsCopyLoweringPass::rewriteSe .addReg(Reg) .addImm(SubRegIdx[OrigRegSize]); } else if (OrigRegSize > TargetRegSize) { - BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::EXTRACT_SUBREG), + if (TargetRegSize == 1 && !Subtarget->is64Bit()) { + // Need to constrain the register class. + MRI->constrainRegClass(Reg, &X86::GR32_ABCDRegClass); + } + + BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg) - .addReg(Reg) - .addImm(SubRegIdx[TargetRegSize]); + .addReg(Reg, 0, SubRegIdx[TargetRegSize]); } else { BuildMI(MBB, SetPos, SetLoc, TII->get(TargetOpcode::COPY), NewReg) .addReg(Reg); Modified: llvm/branches/release_70/test/CodeGen/X86/flags-copy-lowering.mir URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/X86/flags-copy-lowering.mir?rev=339999&r1=339998&r2=339999&view=diff ============================================================================== --- llvm/branches/release_70/test/CodeGen/X86/flags-copy-lowering.mir (original) +++ llvm/branches/release_70/test/CodeGen/X86/flags-copy-lowering.mir Fri Aug 17 00:38:52 2018 @@ -545,7 +545,7 @@ body: | MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %4 ; CHECK-NOT: $eflags = ; CHECK: %[[ZERO:[^:]*]]:gr32 = MOV32r0 implicit-def $eflags - ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr8 = EXTRACT_SUBREG %[[ZERO]], %subreg.sub_8bit + ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr8 = COPY %[[ZERO]].sub_8bit ; CHECK-NEXT: %[[REPLACEMENT:[^:]*]]:gr8 = SUB8rr %[[ZERO_SUBREG]], %[[CF_REG]] ; CHECK-NEXT: MOV8mr $rsp, 1, $noreg, -16, $noreg, killed %[[REPLACEMENT]] @@ -554,9 +554,9 @@ body: | MOV16mr $rsp, 1, $noreg, -16, $noreg, killed %5 ; CHECK-NOT: $eflags = ; CHECK: %[[CF_EXT:[^:]*]]:gr32 = MOVZX32rr8 %[[CF_REG]] - ; CHECK-NEXT: %[[CF_TRUNC:[^:]*]]:gr16 = EXTRACT_SUBREG %[[CF_EXT]], %subreg.sub_16bit + ; CHECK-NEXT: %[[CF_TRUNC:[^:]*]]:gr16 = COPY %[[CF_EXT]].sub_16bit ; CHECK-NEXT: %[[ZERO:[^:]*]]:gr32 = MOV32r0 implicit-def $eflags - ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr16 = EXTRACT_SUBREG %[[ZERO]], %subreg.sub_16bit + ; CHECK-NEXT: %[[ZERO_SUBREG:[^:]*]]:gr16 = COPY %[[ZERO]].sub_16bit ; CHECK-NEXT: %[[REPLACEMENT:[^:]*]]:gr16 = SUB16rr %[[ZERO_SUBREG]], %[[CF_TRUNC]] ; CHECK-NEXT: MOV16mr $rsp, 1, $noreg, -16, $noreg, killed %[[REPLACEMENT]] _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
