Author: hans Date: Mon Aug 6 23:23:16 2018 New Revision: 339098 URL: http://llvm.org/viewvc/llvm-project?rev=339098&view=rev Log: Merging r338665: ------------------------------------------------------------------------ r338665 | lliu0 | 2018-08-02 03:54:12 +0200 (Thu, 02 Aug 2018) | 11 lines
Fix FCOPYSIGN expansion In expansion of FCOPYSIGN, the shift node is missing when the two operands of FCOPYSIGN are of the same size. We should always generate shift node (if the required shift bit is not zero) to put the sign bit into the right position, regardless of the size of underlying types. Differential Revision: https://reviews.llvm.org/D49973 ------------------------------------------------------------------------ Modified: llvm/branches/release_70/ (props changed) llvm/branches/release_70/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/branches/release_70/test/CodeGen/AArch64/fcopysign.ll Propchange: llvm/branches/release_70/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Mon Aug 6 23:23:16 2018 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,338552,338554,338599,338658,338682,338703,338709,338751,338762,338817 +/llvm/trunk:155241,338552,338554,338599,338658,338665,338682,338703,338709,338751,338762,338817 Modified: llvm/branches/release_70/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=339098&r1=339097&r2=339098&view=diff ============================================================================== --- llvm/branches/release_70/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/branches/release_70/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Aug 6 23:23:16 2018 @@ -1489,24 +1489,20 @@ SDValue SelectionDAGLegalize::ExpandFCOP // Get the signbit at the right position for MagAsInt. int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; + EVT ShiftVT = IntVT; + if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) { + SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); + ShiftVT = MagVT; + } + if (ShiftAmount > 0) { + SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT); + SignBit = DAG.getNode(ISD::SRL, DL, ShiftVT, SignBit, ShiftCnst); + } else if (ShiftAmount < 0) { + SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT); + SignBit = DAG.getNode(ISD::SHL, DL, ShiftVT, SignBit, ShiftCnst); + } if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) { - if (ShiftAmount > 0) { - SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT); - SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst); - } else if (ShiftAmount < 0) { - SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT); - SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst); - } SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit); - } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) { - SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit); - if (ShiftAmount > 0) { - SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT); - SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst); - } else if (ShiftAmount < 0) { - SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT); - SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst); - } } // Store the part with the modified sign and convert back to float. Modified: llvm/branches/release_70/test/CodeGen/AArch64/fcopysign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_70/test/CodeGen/AArch64/fcopysign.ll?rev=339098&r1=339097&r2=339098&view=diff ============================================================================== --- llvm/branches/release_70/test/CodeGen/AArch64/fcopysign.ll (original) +++ llvm/branches/release_70/test/CodeGen/AArch64/fcopysign.ll Mon Aug 6 23:23:16 2018 @@ -5,10 +5,12 @@ target triple = "aarch64--" declare fp128 @llvm.copysign.f128(fp128, fp128) -@val = global double zeroinitializer, align 8 +@val_float = global float zeroinitializer, align 4 +@val_double = global double zeroinitializer, align 8 +@val_fp128 = global fp128 zeroinitializer, align 16 ; CHECK-LABEL: copysign0 -; CHECK: ldr [[REG:x[0-9]+]], [x8, :lo12:val] +; CHECK: ldr [[REG:x[0-9]+]], [x8, :lo12:val_double] ; CHECK: and [[ANDREG:x[0-9]+]], [[REG]], #0x8000000000000000 ; CHECK: lsr x[[LSRREGNUM:[0-9]+]], [[ANDREG]], #56 ; CHECK: bfxil w[[LSRREGNUM]], w{{[0-9]+}}, #0, #7 @@ -16,8 +18,25 @@ declare fp128 @llvm.copysign.f128(fp128, ; CHECK: ldr q{{[0-9]+}}, define fp128 @copysign0() { entry: - %v = load double, double* @val, align 8 + %v = load double, double* @val_double, align 8 %conv = fpext double %v to fp128 %call = tail call fp128 @llvm.copysign.f128(fp128 0xL00000000000000007FFF000000000000, fp128 %conv) #2 ret fp128 %call } + +; CHECK-LABEL: copysign1 +; CHECK-DAG: ldr [[REG:q[0-9]+]], [x8, :lo12:val_fp128] +; CHECK-DAG: ldr [[REG:w[0-9]+]], [x8, :lo12:val_float] +; CHECK: and [[ANDREG:w[0-9]+]], [[REG]], #0x80000000 +; CHECK: lsr w[[LSRREGNUM:[0-9]+]], [[ANDREG]], #24 +; CHECK: bfxil w[[LSRREGNUM]], w{{[0-9]+}}, #0, #7 +; CHECK: strb w[[LSRREGNUM]], +; CHECK: ldr q{{[0-9]+}}, +define fp128@copysign1() { +entry: + %v0 = load fp128, fp128* @val_fp128, align 16 + %v1 = load float, float* @val_float, align 4 + %conv = fpext float %v1 to fp128 + %call = tail call fp128 @llvm.copysign.f128(fp128 %v0, fp128 %conv) + ret fp128 %call +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
