Author: chandlerc
Date: Mon May 21 19:53:53 2018
New Revision: 332937
URL: http://llvm.org/viewvc/llvm-project?rev=332937&view=rev
Log:
Merge r329771, fixing $regname to be %regname.
Modified:
llvm/branches/release_60/ (props changed)
llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir
Propchange: llvm/branches/release_60/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon May 21 19:53:53 2018
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673
+/llvm/trunk:155241,321751,321789,321791,321806,321862,321870,321872,321878,321911,321980,321991,321993-321994,322003,322016,322053,322056,322103,322106,322108,322123,322131,322223,322272,322313,322372,322473,322521,322623,322644,322724,322767,322875,322878-322879,322900,322904-322905,322973,322993,323034,323155,323190,323307,323331,323355,323369,323371,323384,323469,323515,323536,323582,323643,323671-323672,323706,323710,323759,323781,323810-323811,323813,323857,323907-323909,323913,323915,324002,324039,324110,324195,324353,324422,324449,324497,324576,324645,324746,324772,324916,324962,325049,325085,325139,325148,325168,325463,325525,325550,325654,325687,325739,325894,325946,326393,328945,329040,329055-329057,329657,329673,329771
Modified: llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp?rev=332937&r1=332936&r2=332937&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86FlagsCopyLowering.cpp Mon May 21
19:53:53 2018
@@ -727,8 +727,27 @@ void X86FlagsCopyLoweringPass::rewriteSe
if (!CondReg)
CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond);
- // Rewriting this is trivial: we just replace the register and remove the
- // setcc.
- MRI->replaceRegWith(SetCCI.getOperand(0).getReg(), CondReg);
+ // Rewriting a register def is trivial: we just replace the register and
+ // remove the setcc.
+ if (!SetCCI.mayStore()) {
+ assert(SetCCI.getOperand(0).isReg() &&
+ "Cannot have a non-register defined operand to SETcc!");
+ MRI->replaceRegWith(SetCCI.getOperand(0).getReg(), CondReg);
+ SetCCI.eraseFromParent();
+ return;
+ }
+
+ // Otherwise, we need to emit a store.
+ auto MIB = BuildMI(*SetCCI.getParent(), SetCCI.getIterator(),
+ SetCCI.getDebugLoc(), TII->get(X86::MOV8mr));
+ // Copy the address operands.
+ for (int i = 0; i < X86::AddrNumOperands; ++i)
+ MIB.add(SetCCI.getOperand(i));
+
+ MIB.addReg(CondReg);
+
+ MIB->setMemRefs(SetCCI.memoperands_begin(), SetCCI.memoperands_end());
+
SetCCI.eraseFromParent();
+ return;
}
Modified: llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir?rev=332937&r1=332936&r2=332937&view=diff
==============================================================================
--- llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir (original)
+++ llvm/branches/release_60/test/CodeGen/X86/flags-copy-lowering.mir Mon May
21 19:53:53 2018
@@ -208,11 +208,10 @@ body: |
%3:gr8 = SETAr implicit %eflags
%4:gr8 = SETBr implicit %eflags
%5:gr8 = SETEr implicit %eflags
- %6:gr8 = SETNEr implicit killed %eflags
+ SETNEm %rsp, 1, %noreg, -16, %noreg, implicit killed %eflags
MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %3
MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %4
MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %5
- MOV8mr %rsp, 1, %noreg, -16, %noreg, killed %6
; CHECK-NOT: %eflags =
; CHECK-NOT: = SET{{.*}}
; CHECK: MOV8mr {{.*}}, killed %[[A_REG]]
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