Author: tstellar
Date: Fri May 18 14:58:58 2018
New Revision: 332776
URL: http://llvm.org/viewvc/llvm-project?rev=332776&view=rev
Log:
Merging r324885:
------------------------------------------------------------------------
r324885 | atanasyan | 2018-02-12 04:21:55 -0800 (Mon, 12 Feb 2018) | 8 lines
[mips] Fix 'l' constraint handling for types smaller than 32 bits
In case of correct using of the 'l' constraint llvm now generates valid
code; otherwise it shows an error message. Initially these triggers an
assertion.
This commit is the same as r324869 with fixed the test's file name.
------------------------------------------------------------------------
Added:
llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll
Modified:
llvm/branches/release_60/lib/Target/Mips/MipsISelLowering.cpp
llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
Modified: llvm/branches/release_60/lib/Target/Mips/MipsISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/Mips/MipsISelLowering.cpp?rev=332776&r1=332775&r2=332776&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/branches/release_60/lib/Target/Mips/MipsISelLowering.cpp Fri May 18
14:58:58 2018
@@ -3868,7 +3868,7 @@ MipsTargetLowering::getRegForInlineAsmCo
return std::make_pair(0U, nullptr);
case 'l': // use the `lo` register to store values
// that are no bigger than a word
- if (VT == MVT::i32)
+ if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
case 'x': // use the concatenated `hi` and `lo` registers
Added: llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll?rev=332776&view=auto
==============================================================================
--- llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll
(added)
+++ llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-bad-l1.ll Fri
May 18 14:58:58 2018
@@ -0,0 +1,13 @@
+; Negative test. The constraint 'l' represents the register 'lo'.
+; Check error message in case of invalid usage.
+;
+; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s
+
+define void @constraint_l() nounwind {
+entry:
+
+; CHECK: error: invalid operand for instruction
+
+ tail call i16 asm sideeffect "addiu $0,$1,$2", "=l,r,r,~{$1}"(i16 0, i16 0)
+ ret void
+}
Modified: llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll?rev=332776&r1=332775&r2=332776&view=diff
==============================================================================
--- llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll
(original)
+++ llvm/branches/release_60/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll Fri May
18 14:58:58 2018
@@ -41,5 +41,15 @@ entry:
call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32
7, i32 6, i32 44) nounwind
store volatile i32 %4, i32* %bosco, align 4
+; Check the 'l' constraint for 16-bit type.
+; CHECK: #APP
+; CHECK: mtlo ${{[0-9]+}}
+; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
+; CHECK: #NO_APP
+; CHECK-NEXT: mflo ${{[0-9]+}}
+ %bosco16 = alloca i16, align 4
+ call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32
7, i32 6, i32 44) nounwind
+ store volatile i16 %5, i16* %bosco16, align 4
+
ret i32 0
}
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