Author: tstellar
Date: Wed May 16 19:15:22 2018
New Revision: 332564
URL: http://llvm.org/viewvc/llvm-project?rev=332564&view=rev
Log:
Merging r328944:
------------------------------------------------------------------------
r328944 | chandlerc | 2018-04-01 14:47:55 -0700 (Sun, 01 Apr 2018) | 4 lines
[x86] Expose more of the condition conversion routines in the public API
for X86's instruction information. I've now got a second patch under
review that needs these same APIs. This bit is nicely orthogonal and
obvious, so landing it. NFC.
------------------------------------------------------------------------
Modified:
llvm/branches/release_60/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/release_60/lib/Target/X86/X86InstrInfo.h
Modified: llvm/branches/release_60/lib/Target/X86/X86InstrInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86InstrInfo.cpp?rev=332564&r1=332563&r2=332564&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/release_60/lib/Target/X86/X86InstrInfo.cpp Wed May 16
19:15:22 2018
@@ -5782,7 +5782,7 @@ bool X86InstrInfo::findCommutedOpIndices
return false;
}
-static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
+X86::CondCode X86::getCondFromBranchOpc(unsigned BrOpc) {
switch (BrOpc) {
default: return X86::COND_INVALID;
case X86::JE_1: return X86::COND_E;
@@ -5805,7 +5805,7 @@ static X86::CondCode getCondFromBranchOp
}
/// Return condition code of a SET opcode.
-static X86::CondCode getCondFromSETOpc(unsigned Opc) {
+X86::CondCode X86::getCondFromSETOpc(unsigned Opc) {
switch (Opc) {
default: return X86::COND_INVALID;
case X86::SETAr: case X86::SETAm: return X86::COND_A;
@@ -6130,7 +6130,7 @@ void X86InstrInfo::replaceBranchWithTail
if (!I->isBranch())
assert(0 && "Can't find the branch to replace!");
- X86::CondCode CC = getCondFromBranchOpc(I->getOpcode());
+ X86::CondCode CC = X86::getCondFromBranchOpc(I->getOpcode());
assert(BranchCond.size() == 1);
if (CC != BranchCond[0].getImm())
continue;
@@ -6237,7 +6237,7 @@ bool X86InstrInfo::AnalyzeBranchImpl(
}
// Handle conditional branches.
- X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
+ X86::CondCode BranchCode = X86::getCondFromBranchOpc(I->getOpcode());
if (BranchCode == X86::COND_INVALID)
return true; // Can't handle indirect branch.
@@ -6433,7 +6433,7 @@ unsigned X86InstrInfo::removeBranch(Mach
if (I->isDebugValue())
continue;
if (I->getOpcode() != X86::JMP_1 &&
- getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
+ X86::getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
break;
// Remove the branch.
I->eraseFromParent();
@@ -7465,9 +7465,9 @@ bool X86InstrInfo::optimizeCompareInstr(
if (IsCmpZero || IsSwapped) {
// We decode the condition code from opcode.
if (Instr.isBranch())
- OldCC = getCondFromBranchOpc(Instr.getOpcode());
+ OldCC = X86::getCondFromBranchOpc(Instr.getOpcode());
else {
- OldCC = getCondFromSETOpc(Instr.getOpcode());
+ OldCC = X86::getCondFromSETOpc(Instr.getOpcode());
if (OldCC != X86::COND_INVALID)
OpcIsSET = true;
else
Modified: llvm/branches/release_60/lib/Target/X86/X86InstrInfo.h
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/lib/Target/X86/X86InstrInfo.h?rev=332564&r1=332563&r2=332564&view=diff
==============================================================================
--- llvm/branches/release_60/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/release_60/lib/Target/X86/X86InstrInfo.h Wed May 16 19:15:22
2018
@@ -77,6 +77,12 @@ unsigned getSETFromCond(CondCode CC, boo
unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
bool HasMemoryOperand = false);
+// Turn jCC opcode into condition code.
+CondCode getCondFromBranchOpc(unsigned Opc);
+
+// Turn setCC opcode into condition code.
+CondCode getCondFromSETOpc(unsigned Opc);
+
// Turn CMov opcode into condition code.
CondCode getCondFromCMovOpc(unsigned Opc);
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