Author: ctopper
Date: Fri Feb 23 10:33:04 2018
New Revision: 325932
URL: http://llvm.org/viewvc/llvm-project?rev=325932&view=rev
Log:
[ReleaseNotes] More X86 updates
Modified:
llvm/branches/release_60/docs/ReleaseNotes.rst
Modified: llvm/branches/release_60/docs/ReleaseNotes.rst
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_60/docs/ReleaseNotes.rst?rev=325932&r1=325931&r2=325932&view=diff
==============================================================================
--- llvm/branches/release_60/docs/ReleaseNotes.rst (original)
+++ llvm/branches/release_60/docs/ReleaseNotes.rst Fri Feb 23 10:33:04 2018
@@ -178,14 +178,34 @@ During this release the X86 target has:
* Added support for Intel Icelake CPU.
+* Fixed some X87 codegen bugs.
+
* Added instruction scheduling information for Intel Sandy Bridge, Ivy Bridge,
Haswell, Broadwell, and Skylake CPUs.
-* Improved codegen of data being transferred between GPRs and K-registers.
+* Improved scheduler model for AMD Jaguar CPUs.
* Improved llvm-mc's disassembler for some EVEX encoded instructions.
+* Add support for i8 and i16 vector signed/unsigned min/max horizontal
reductions.
+
+* Improved codegen for memory comparisons
+
+* Improved codegen for i32 vector multiplies
+
+* Improved codegen for scalar integer absolute values
+
+* Improved codegen for vector integer rotations (XOP and AVX512)
+
+* Improved codegen of data being transferred between GPRs and K-registers.
+
* Improved codegen for vector truncations.
+* Improved folding of address computations into gather/scatter instructions.
+
+* Gained initial support recognizing variable shuffles from vector element
extracts and inserts.
+
+* Improved documentation for SSE/AVX intrinsics in *intrin.h header files.
+
Changes to the AMDGPU Target
-----------------------------
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
