Author: kparzysz
Date: Thu Apr 27 10:38:30 2017
New Revision: 301550
URL: http://llvm.org/viewvc/llvm-project?rev=301550&view=rev
Log:
Merging r296645: (PR32253)
Included an updated testcase
------------------------------------------------------------------------
[Hexagon] Fix lowering of formal arguments of type i1
On Hexagon, values of type i1 are passed in registers of type i32,
even though i1 is not a legal value for these registers. This is a
special case and needs special handling to maintain consistency of
the lowering information.
This fixes PR32089.
------------------------------------------------------------------------
Added:
llvm/branches/release_40/test/CodeGen/Hexagon/isel-i1arg-crash.ll
Modified:
llvm/branches/release_40/lib/Target/Hexagon/HexagonISelLowering.cpp
llvm/branches/release_40/test/MC/Hexagon/inst_select.ll
Modified: llvm/branches/release_40/lib/Target/Hexagon/HexagonISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=301550&r1=301549&r2=301550&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/Hexagon/HexagonISelLowering.cpp
(original)
+++ llvm/branches/release_40/lib/Target/Hexagon/HexagonISelLowering.cpp Thu Apr
27 10:38:30 2017
@@ -256,7 +256,9 @@ static bool CC_Hexagon (unsigned ValNo,
return false;
}
- if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
+ if (LocVT == MVT::i1) {
+ LocVT = MVT::i32;
+ } else if (LocVT == MVT::i8 || LocVT == MVT::i16) {
LocVT = MVT::i32;
ValVT = MVT::i32;
if (ArgFlags.isSExt())
@@ -1140,10 +1142,25 @@ SDValue HexagonTargetLowering::LowerForm
EVT RegVT = VA.getLocVT();
if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
RegVT == MVT::i32 || RegVT == MVT::f32) {
- unsigned VReg =
+ unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
RegInfo.addLiveIn(VA.getLocReg(), VReg);
- InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
+ SDValue Copy = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
+ // Treat values of type MVT::i1 specially: they are passed in
+ // registers of type i32, but they need to remain as values of
+ // type i1 for consistency of the argument lowering.
+ if (VA.getValVT() == MVT::i1) {
+ // Generate a copy into a predicate register and use the value
+ // of the register as the "InVal".
+ unsigned PReg =
+ RegInfo.createVirtualRegister(&Hexagon::PredRegsRegClass);
+ SDNode *T = DAG.getMachineNode(Hexagon::C2_tfrrp, dl, MVT::i1,
+ Copy.getValue(0));
+ Copy = DAG.getCopyToReg(Copy.getValue(1), dl, PReg, SDValue(T, 0));
+ Copy = DAG.getCopyFromReg(Copy, dl, PReg, MVT::i1);
+ }
+ InVals.push_back(Copy);
+ Chain = Copy.getValue(1);
} else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
unsigned VReg =
RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
Added: llvm/branches/release_40/test/CodeGen/Hexagon/isel-i1arg-crash.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/Hexagon/isel-i1arg-crash.ll?rev=301550&view=auto
==============================================================================
--- llvm/branches/release_40/test/CodeGen/Hexagon/isel-i1arg-crash.ll (added)
+++ llvm/branches/release_40/test/CodeGen/Hexagon/isel-i1arg-crash.ll Thu Apr
27 10:38:30 2017
@@ -0,0 +1,6 @@
+; RUN: llc -march=hexagon -debug-only=isel < %s
+; REQUIRES: asserts
+
+define void @g(i1 %cond) {
+ ret void
+}
Modified: llvm/branches/release_40/test/MC/Hexagon/inst_select.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/MC/Hexagon/inst_select.ll?rev=301550&r1=301549&r2=301550&view=diff
==============================================================================
--- llvm/branches/release_40/test/MC/Hexagon/inst_select.ll (original)
+++ llvm/branches/release_40/test/MC/Hexagon/inst_select.ll Thu Apr 27 10:38:30
2017
@@ -7,7 +7,7 @@ define i32 @foo (i1 %a, i32 %b, i32 %c)
ret i32 %1
}
-; CHECK: 00 40 00 85 85004000
+; CHECK: 00 40 40 85 85404000
; CHECK: 00 40 9f 52 529f4000
; CHECK: 00 60 01 74 74016000
-; CHECK: 00 e0 82 74 7482e000
\ No newline at end of file
+; CHECK: 00 e0 82 74 7482e000
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