Author: hans
Date: Tue Feb 14 19:06:12 2017
New Revision: 295135
URL: http://llvm.org/viewvc/llvm-project?rev=295135&view=rev
Log:
Merging r294527:
------------------------------------------------------------------------
r294527 | arnolds | 2017-02-08 14:30:47 -0800 (Wed, 08 Feb 2017) | 14 lines
[ARM/AArch ISel] SwiftCC: First parameters that are marked swiftself are not
'this returns'
We mark X0 as preserved by a call that passes the returned parameter.
x0 = ...
fun(x0) // no implicit def of x0
This no longer is valid if we pass the parameter in a different register then
the returned value as is the case with a swiftself parameter (passed in x20).
x20 = ...
fun(x20) // there should be an implict def of x8
rdar://30425845
------------------------------------------------------------------------
Modified:
llvm/branches/release_40/ (props changed)
llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/release_40/test/CodeGen/AArch64/swiftself.ll
llvm/branches/release_40/test/CodeGen/ARM/swiftself.ll
Propchange: llvm/branches/release_40/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Tue Feb 14 19:06:12 2017
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,291858-291859,291863,291875,291909,291918,291966,291968,291979,292117,292133,292167,292169-292170,292242,292254-292255,292280,292323,292444,292467,292516,292583,292624-292625,292641,292651,292667,292711-292713,292758,292949,293017,293021,293025,293230,293259,293291,293293,293309,293345,293417,293522,293542,293629,293635,293658,293673,293727,293730,294102,294203,294267,294318,294348-294349,294357,294551,295018
+/llvm/trunk:155241,291858-291859,291863,291875,291909,291918,291966,291968,291979,292117,292133,292167,292169-292170,292242,292254-292255,292280,292323,292444,292467,292516,292583,292624-292625,292641,292651,292667,292711-292713,292758,292949,293017,293021,293025,293230,293259,293291,293293,293309,293345,293417,293522,293542,293629,293635,293658,293673,293727,293730,294102,294203,294267,294318,294348-294349,294357,294527,294551,295018
Modified: llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=295135&r1=295134&r2=295135&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp
(original)
+++ llvm/branches/release_40/lib/Target/AArch64/AArch64ISelLowering.cpp Tue Feb
14 19:06:12 2017
@@ -3155,7 +3155,8 @@ AArch64TargetLowering::LowerCall(CallLow
}
if (VA.isRegLoc()) {
- if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i64) {
+ if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
+ Outs[0].VT == MVT::i64) {
assert(VA.getLocVT() == MVT::i64 &&
"unexpected calling convention register assignment");
assert(!Ins.empty() && Ins[0].VT == MVT::i64 &&
Modified: llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp?rev=295135&r1=295134&r2=295135&view=diff
==============================================================================
--- llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/release_40/lib/Target/ARM/ARMISelLowering.cpp Tue Feb 14
19:06:12 2017
@@ -1787,7 +1787,8 @@ ARMTargetLowering::LowerCall(TargetLower
StackPtr, MemOpChains, Flags);
}
} else if (VA.isRegLoc()) {
- if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
+ if (realArgIdx == 0 && Flags.isReturned() && !Flags.isSwiftSelf() &&
+ Outs[0].VT == MVT::i32) {
assert(VA.getLocVT() == MVT::i32 &&
"unexpected calling convention register assignment");
assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
Modified: llvm/branches/release_40/test/CodeGen/AArch64/swiftself.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/AArch64/swiftself.ll?rev=295135&r1=295134&r2=295135&view=diff
==============================================================================
--- llvm/branches/release_40/test/CodeGen/AArch64/swiftself.ll (original)
+++ llvm/branches/release_40/test/CodeGen/AArch64/swiftself.ll Tue Feb 14
19:06:12 2017
@@ -65,3 +65,21 @@ define i8* @swiftself_notail(i8* swiftse
%res = tail call i8* @swiftself_param(i8* swiftself %addr1)
ret i8* %res
}
+
+; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as
+; we normally would. We marked the first parameter with swiftself which means
it
+; will no longer be passed in x0.
+declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
+; OPT-LABEL: swiftself_nothisreturn:
+; OPT-DAG: ldr x20, [x20]
+; OPT-DAG: mov [[CSREG:x[1-9].*]], x8
+; OPT: bl {{_?}}thisreturn_attribute
+; OPT: str x0, {{\[}}[[CSREG]]
+; OPT: ret
+define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture
sret, i8** noalias nocapture readonly swiftself) {
+entry:
+ %2 = load i8*, i8** %1, align 8
+ %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
+ store i8* %3, i8** %0, align 8
+ ret void
+}
Modified: llvm/branches/release_40/test/CodeGen/ARM/swiftself.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/ARM/swiftself.ll?rev=295135&r1=295134&r2=295135&view=diff
==============================================================================
--- llvm/branches/release_40/test/CodeGen/ARM/swiftself.ll (original)
+++ llvm/branches/release_40/test/CodeGen/ARM/swiftself.ll Tue Feb 14 19:06:12
2017
@@ -63,3 +63,20 @@ define i8* @swiftself_notail(i8* swiftse
%res = tail call i8* @swiftself_param(i8* swiftself %addr1)
ret i8* %res
}
+
+; We cannot pretend that 'r0' is alive across the thisreturn_attribute call as
+; we normally would. We marked the first parameter with swiftself which means
it
+; will no longer be passed in r0.
+declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
+; OPT-LABEL: swiftself_nothisreturn:
+; OPT-DAG: mov [[CSREG:r[1-9].*]], r0
+; OPT-DAG: ldr r10, [r10]
+; OPT: bl {{_?}}thisreturn_attribute
+; OPT: str r0, {{\[}}[[CSREG]]
+define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture
sret, i8** noalias nocapture readonly swiftself) {
+entry:
+ %2 = load i8*, i8** %1, align 8
+ %3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
+ store i8* %3, i8** %0, align 8
+ ret void
+}
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