(For my notes, this is a merge of r292954.)
On Fri, Jan 27, 2017 at 12:57 PM, Evandro Menezes via llvm-branch-commits <llvm-branch-commits@lists.llvm.org> wrote: > Author: evandro > Date: Fri Jan 27 14:57:35 2017 > New Revision: 293332 > > URL: http://llvm.org/viewvc/llvm-project?rev=293332&view=rev > Log: > [AArch64] Rename 'no-quad-ldst-pairs' to 'slow-paired-128' > > In order to follow the pattern of the existing 'slow-misaligned-128store' > option, rename the option 'no-quad-ldst-pairs' to 'slow-paired-128'. > > > Modified: > llvm/branches/release_40/lib/Target/AArch64/AArch64.td > llvm/branches/release_40/lib/Target/AArch64/AArch64InstrInfo.cpp > llvm/branches/release_40/lib/Target/AArch64/AArch64Subtarget.h > llvm/branches/release_40/test/CodeGen/AArch64/no-quad-ldp-stp.ll > > Modified: llvm/branches/release_40/lib/Target/AArch64/AArch64.td > URL: > http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AArch64/AArch64.td?rev=293332&r1=293331&r2=293332&view=diff > ============================================================================== > --- llvm/branches/release_40/lib/Target/AArch64/AArch64.td (original) > +++ llvm/branches/release_40/lib/Target/AArch64/AArch64.td Fri Jan 27 > 14:57:35 2017 > @@ -85,9 +85,8 @@ def FeaturePostRAScheduler : SubtargetFe > def FeatureSlowMisaligned128Store : > SubtargetFeature<"slow-misaligned-128store", > "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are > slow">; > > -def FeatureAvoidQuadLdStPairs : SubtargetFeature<"no-quad-ldst-pairs", > - "AvoidQuadLdStPairs", "true", > - "Do not form quad load/store pair operations">; > +def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128", > + "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">; > > def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature< > "alternate-sextload-cvt-f32-pattern", > "UseAlternateSExtLoadCVTF32Pattern", > @@ -222,7 +221,7 @@ def ProcCyclone : SubtargetFeature<"cycl > > def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1", > "Samsung Exynos-M1 processors", > - [FeatureAvoidQuadLdStPairs, > + [FeatureSlowPaired128, > FeatureCRC, > FeatureCrypto, > FeatureCustomCheapAsMoveHandling, > @@ -236,7 +235,7 @@ def ProcExynosM1 : SubtargetFeature<"exy > > def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1", > "Samsung Exynos-M2/M3 processors", > - [FeatureAvoidQuadLdStPairs, > + [FeatureSlowPaired128, > FeatureCRC, > FeatureCrypto, > FeatureCustomCheapAsMoveHandling, > > Modified: llvm/branches/release_40/lib/Target/AArch64/AArch64InstrInfo.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=293332&r1=293331&r2=293332&view=diff > ============================================================================== > --- llvm/branches/release_40/lib/Target/AArch64/AArch64InstrInfo.cpp > (original) > +++ llvm/branches/release_40/lib/Target/AArch64/AArch64InstrInfo.cpp Fri Jan > 27 14:57:35 2017 > @@ -1652,7 +1652,7 @@ bool AArch64InstrInfo::isCandidateToMerg > return false; > > // On some CPUs quad load/store pairs are slower than two single > load/stores. > - if (Subtarget.avoidQuadLdStPairs()) { > + if (Subtarget.isPaired128Slow()) { > switch (MI.getOpcode()) { > default: > break; > > Modified: llvm/branches/release_40/lib/Target/AArch64/AArch64Subtarget.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/lib/Target/AArch64/AArch64Subtarget.h?rev=293332&r1=293331&r2=293332&view=diff > ============================================================================== > --- llvm/branches/release_40/lib/Target/AArch64/AArch64Subtarget.h (original) > +++ llvm/branches/release_40/lib/Target/AArch64/AArch64Subtarget.h Fri Jan 27 > 14:57:35 2017 > @@ -79,7 +79,7 @@ protected: > bool CustomAsCheapAsMove = false; > bool UsePostRAScheduler = false; > bool Misaligned128StoreIsSlow = false; > - bool AvoidQuadLdStPairs = false; > + bool Paired128IsSlow = false; > bool UseAlternateSExtLoadCVTF32Pattern = false; > bool HasArithmeticBccFusion = false; > bool HasArithmeticCbzFusion = false; > @@ -189,7 +189,7 @@ public: > } > bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; } > bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; } > - bool avoidQuadLdStPairs() const { return AvoidQuadLdStPairs; } > + bool isPaired128Slow() const { return Paired128IsSlow; } > bool useAlternateSExtLoadCVTF32Pattern() const { > return UseAlternateSExtLoadCVTF32Pattern; > } > > Modified: llvm/branches/release_40/test/CodeGen/AArch64/no-quad-ldp-stp.ll > URL: > http://llvm.org/viewvc/llvm-project/llvm/branches/release_40/test/CodeGen/AArch64/no-quad-ldp-stp.ll?rev=293332&r1=293331&r2=293332&view=diff > ============================================================================== > --- llvm/branches/release_40/test/CodeGen/AArch64/no-quad-ldp-stp.ll > (original) > +++ llvm/branches/release_40/test/CodeGen/AArch64/no-quad-ldp-stp.ll Fri Jan > 27 14:57:35 2017 > @@ -1,4 +1,4 @@ > -; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+no-quad-ldst-pairs > -verify-machineinstrs -asm-verbose=false | FileCheck %s > +; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+slow-paired-128 > -verify-machineinstrs -asm-verbose=false | FileCheck %s > ; RUN: llc < %s -mtriple=aarch64-eabi -mcpu=exynos-m1 -verify-machineinstrs > -asm-verbose=false | FileCheck %s > > ; CHECK-LABEL: test_nopair_st > > > _______________________________________________ > llvm-branch-commits mailing list > llvm-branch-commits@lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
