Author: hans Date: Thu Aug 18 14:43:50 2016 New Revision: 279123 URL: http://llvm.org/viewvc/llvm-project?rev=279123&view=rev Log: Merging r278559: ------------------------------------------------------------------------ r278559 | efriedma | 2016-08-12 13:28:02 -0700 (Fri, 12 Aug 2016) | 7 lines
[AArch64LoadStoreOpt] Handle offsets correctly for post-indexed paired loads. Trunk would try to create something like "stp x9, x8, [x0], #512", which isn't actually a valid instruction. Differential revision: https://reviews.llvm.org/D23368 ------------------------------------------------------------------------ Modified: llvm/branches/release_39/ (props changed) llvm/branches/release_39/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp llvm/branches/release_39/test/CodeGen/AArch64/ldst-opt.ll Propchange: llvm/branches/release_39/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Aug 18 14:43:50 2016 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276051,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276676,276712,276740,276823,276956,276980,277093,277114,277135,277371,277399,277500,277504,277625,277691,277693,277773,278002,278086,278133,278157,278370,278413,278558,278562,278569,278571,278573,278575,278584,278841,278900,278938,278999 +/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276051,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276676,276712,276740,276823,276956,276980,277093,277114,277135,277371,277399,277500,277504,277625,277691,277693,277773,278002,278086,278133,278157,278370,278413,278558-278559,278562,278569,278571,278573,278575,278584,278841,278900,278938,278999 Modified: llvm/branches/release_39/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp?rev=279123&r1=279122&r2=279123&view=diff ============================================================================== --- llvm/branches/release_39/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp (original) +++ llvm/branches/release_39/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp Thu Aug 18 14:43:50 2016 @@ -1427,9 +1427,6 @@ bool AArch64LoadStoreOpt::isMatchingUpda default: break; case AArch64::SUBXri: - // Negate the offset for a SUB instruction. - Offset *= -1; - // FALLTHROUGH case AArch64::ADDXri: // Make sure it's a vanilla immediate operand, not a relocation or // anything else we can't handle. @@ -1447,6 +1444,9 @@ bool AArch64LoadStoreOpt::isMatchingUpda bool IsPairedInsn = isPairedLdSt(MemMI); int UpdateOffset = MI.getOperand(2).getImm(); + if (MI.getOpcode() == AArch64::SUBXri) + UpdateOffset = -UpdateOffset; + // For non-paired load/store instructions, the immediate must fit in a // signed 9-bit integer. if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256)) @@ -1461,13 +1461,13 @@ bool AArch64LoadStoreOpt::isMatchingUpda break; int ScaledOffset = UpdateOffset / Scale; - if (ScaledOffset > 64 || ScaledOffset < -64) + if (ScaledOffset > 63 || ScaledOffset < -64) break; } // If we have a non-zero Offset, we check that it matches the amount // we're adding to the register. - if (!Offset || Offset == MI.getOperand(2).getImm()) + if (!Offset || Offset == UpdateOffset) return true; break; } Modified: llvm/branches/release_39/test/CodeGen/AArch64/ldst-opt.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/test/CodeGen/AArch64/ldst-opt.ll?rev=279123&r1=279122&r2=279123&view=diff ============================================================================== --- llvm/branches/release_39/test/CodeGen/AArch64/ldst-opt.ll (original) +++ llvm/branches/release_39/test/CodeGen/AArch64/ldst-opt.ll Thu Aug 18 14:43:50 2016 @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnu -aarch64-atomic-cfg-tidy=0 -disable-lsr -verify-machineinstrs -o - %s | FileCheck %s ; This file contains tests for the AArch64 load/store optimizer. @@ -1230,5 +1230,106 @@ for.body: %cond = icmp sgt i64 %dec.i, 0 br i1 %cond, label %for.body, label %end end: + ret void +} + +define void @post-indexed-sub-doubleword-offset-min(i64* %a, i64* %b, i64 %count) nounwind { +; CHECK-LABEL: post-indexed-sub-doubleword-offset-min +; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}], #-256 +; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}], #-256 + br label %for.body +for.body: + %phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ] + %phi2 = phi i64* [ %gep3, %for.body ], [ %a, %0 ] + %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] + %gep1 = getelementptr i64, i64* %phi1, i64 1 + %load1 = load i64, i64* %gep1 + %gep2 = getelementptr i64, i64* %phi2, i64 1 + store i64 %load1, i64* %gep2 + %load2 = load i64, i64* %phi1 + store i64 %load2, i64* %phi2 + %dec.i = add nsw i64 %i, -1 + %gep3 = getelementptr i64, i64* %phi2, i64 -32 + %gep4 = getelementptr i64, i64* %phi1, i64 -32 + %cond = icmp sgt i64 %dec.i, 0 + br i1 %cond, label %for.body, label %end +end: + ret void +} + +define void @post-indexed-doubleword-offset-out-of-range(i64* %a, i64* %b, i64 %count) nounwind { +; CHECK-LABEL: post-indexed-doubleword-offset-out-of-range +; CHECK: ldr x{{[0-9]+}}, [x{{[0-9]+}}] +; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #256 +; CHECK: str x{{[0-9]+}}, [x{{[0-9]+}}] +; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #256 + + br label %for.body +for.body: + %phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ] + %phi2 = phi i64* [ %gep3, %for.body ], [ %a, %0 ] + %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] + %gep1 = getelementptr i64, i64* %phi1, i64 1 + %load1 = load i64, i64* %gep1 + %gep2 = getelementptr i64, i64* %phi2, i64 1 + store i64 %load1, i64* %gep2 + %load2 = load i64, i64* %phi1 + store i64 %load2, i64* %phi2 + %dec.i = add nsw i64 %i, -1 + %gep3 = getelementptr i64, i64* %phi2, i64 32 + %gep4 = getelementptr i64, i64* %phi1, i64 32 + %cond = icmp sgt i64 %dec.i, 0 + br i1 %cond, label %for.body, label %end +end: + ret void +} + +define void @post-indexed-paired-min-offset(i64* %a, i64* %b, i64 %count) nounwind { +; CHECK-LABEL: post-indexed-paired-min-offset +; CHECK: ldp x{{[0-9]+}}, x{{[0-9]+}}, [x{{[0-9]+}}], #-512 +; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x{{[0-9]+}}], #-512 + br label %for.body +for.body: + %phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ] + %phi2 = phi i64* [ %gep3, %for.body ], [ %a, %0 ] + %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] + %gep1 = getelementptr i64, i64* %phi1, i64 1 + %load1 = load i64, i64* %gep1 + %gep2 = getelementptr i64, i64* %phi2, i64 1 + %load2 = load i64, i64* %phi1 + store i64 %load1, i64* %gep2 + store i64 %load2, i64* %phi2 + %dec.i = add nsw i64 %i, -1 + %gep3 = getelementptr i64, i64* %phi2, i64 -64 + %gep4 = getelementptr i64, i64* %phi1, i64 -64 + %cond = icmp sgt i64 %dec.i, 0 + br i1 %cond, label %for.body, label %end +end: + ret void +} + +define void @post-indexed-paired-offset-out-of-range(i64* %a, i64* %b, i64 %count) nounwind { +; CHECK-LABEL: post-indexed-paired-offset-out-of-range +; CHECK: ldp x{{[0-9]+}}, x{{[0-9]+}}, [x{{[0-9]+}}] +; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #512 +; CHECK: stp x{{[0-9]+}}, x{{[0-9]+}}, [x{{[0-9]+}}] +; CHECK: add x{{[0-9]+}}, x{{[0-9]+}}, #512 + br label %for.body +for.body: + %phi1 = phi i64* [ %gep4, %for.body ], [ %b, %0 ] + %phi2 = phi i64* [ %gep3, %for.body ], [ %a, %0 ] + %i = phi i64 [ %dec.i, %for.body], [ %count, %0 ] + %gep1 = getelementptr i64, i64* %phi1, i64 1 + %load1 = load i64, i64* %phi1 + %gep2 = getelementptr i64, i64* %phi2, i64 1 + %load2 = load i64, i64* %gep1 + store i64 %load1, i64* %gep2 + store i64 %load2, i64* %phi2 + %dec.i = add nsw i64 %i, -1 + %gep3 = getelementptr i64, i64* %phi2, i64 64 + %gep4 = getelementptr i64, i64* %phi1, i64 64 + %cond = icmp sgt i64 %dec.i, 0 + br i1 %cond, label %for.body, label %end +end: ret void } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
