Author: hans Date: Tue Aug 9 10:48:01 2016 New Revision: 278128 URL: http://llvm.org/viewvc/llvm-project?rev=278128&view=rev Log: Merging r278086: ------------------------------------------------------------------------ r278086 | matze | 2016-08-08 18:47:26 -0700 (Mon, 08 Aug 2016) | 6 lines
X86InstrInfo: Update liveness in classifyLea() We need to update liveness information when we create COPYs in classifyLea(). This fixes http://llvm.org/28301 ------------------------------------------------------------------------ Modified: llvm/branches/release_39/ (props changed) llvm/branches/release_39/lib/Target/X86/X86InstrInfo.cpp llvm/branches/release_39/lib/Target/X86/X86InstrInfo.h llvm/branches/release_39/test/CodeGen/X86/twoaddr-lea.ll Propchange: llvm/branches/release_39/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Tue Aug 9 10:48:01 2016 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135,277371,277500,277504,277625,277691,277693,277773 +/llvm/trunk:155241,275868-275870,275879,275898,275928,275935,275946,275978,275981,276015,276077,276109,276119,276181,276209,276236-276237,276358,276364,276368,276389,276435,276438,276479,276510,276648,276740,276956,276980,277114,277135,277371,277500,277504,277625,277691,277693,277773,278086 Modified: llvm/branches/release_39/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/X86/X86InstrInfo.cpp?rev=278128&r1=278127&r2=278128&view=diff ============================================================================== --- llvm/branches/release_39/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/branches/release_39/lib/Target/X86/X86InstrInfo.cpp Tue Aug 9 10:48:01 2016 @@ -2661,7 +2661,8 @@ inline static bool isTruncatedShiftCount bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned Opc, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, - MachineOperand &ImplicitOp) const { + MachineOperand &ImplicitOp, + LiveVariables *LV) const { MachineFunction &MF = *MI.getParent()->getParent(); const TargetRegisterClass *RC; if (AllowSP) { @@ -2715,13 +2716,17 @@ bool X86InstrInfo::classifyLEAReg(Machin // Virtual register of the wrong class, we have to create a temporary 64-bit // vreg to feed into the LEA. NewSrc = MF.getRegInfo().createVirtualRegister(RC); - BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY)) + MachineInstr *Copy = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), + get(TargetOpcode::COPY)) .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) .addOperand(Src); // Which is obviously going to be dead after we're done with it. isKill = true; isUndef = false; + + if (LV) + LV->replaceKillInstruction(SrcReg, MI, *Copy); } // We've set all the parameters without issue. @@ -2900,7 +2905,7 @@ X86InstrInfo::convertToThreeAddress(Mach unsigned SrcReg; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, - SrcReg, isKill, isUndef, ImplicitOp)) + SrcReg, isKill, isUndef, ImplicitOp, LV)) return nullptr; MachineInstrBuilder MIB = @@ -2943,7 +2948,7 @@ X86InstrInfo::convertToThreeAddress(Mach unsigned SrcReg; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, - SrcReg, isKill, isUndef, ImplicitOp)) + SrcReg, isKill, isUndef, ImplicitOp, LV)) return nullptr; MachineInstrBuilder MIB = @@ -2977,7 +2982,7 @@ X86InstrInfo::convertToThreeAddress(Mach unsigned SrcReg; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false, - SrcReg, isKill, isUndef, ImplicitOp)) + SrcReg, isKill, isUndef, ImplicitOp, LV)) return nullptr; MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) @@ -3016,7 +3021,7 @@ X86InstrInfo::convertToThreeAddress(Mach unsigned SrcReg; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, - SrcReg, isKill, isUndef, ImplicitOp)) + SrcReg, isKill, isUndef, ImplicitOp, LV)) return nullptr; const MachineOperand &Src2 = MI.getOperand(2); @@ -3024,7 +3029,7 @@ X86InstrInfo::convertToThreeAddress(Mach unsigned SrcReg2; MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, - SrcReg2, isKill2, isUndef2, ImplicitOp2)) + SrcReg2, isKill2, isUndef2, ImplicitOp2, LV)) return nullptr; MachineInstrBuilder MIB = @@ -3087,7 +3092,7 @@ X86InstrInfo::convertToThreeAddress(Mach unsigned SrcReg; MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false); if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true, - SrcReg, isKill, isUndef, ImplicitOp)) + SrcReg, isKill, isUndef, ImplicitOp, LV)) return nullptr; MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)) Modified: llvm/branches/release_39/lib/Target/X86/X86InstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/lib/Target/X86/X86InstrInfo.h?rev=278128&r1=278127&r2=278128&view=diff ============================================================================== --- llvm/branches/release_39/lib/Target/X86/X86InstrInfo.h (original) +++ llvm/branches/release_39/lib/Target/X86/X86InstrInfo.h Tue Aug 9 10:48:01 2016 @@ -230,7 +230,7 @@ public: bool classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, - MachineOperand &ImplicitOp) const; + MachineOperand &ImplicitOp, LiveVariables *LV) const; /// convertToThreeAddress - This method must be implemented by targets that /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target Modified: llvm/branches/release_39/test/CodeGen/X86/twoaddr-lea.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_39/test/CodeGen/X86/twoaddr-lea.ll?rev=278128&r1=278127&r2=278128&view=diff ============================================================================== --- llvm/branches/release_39/test/CodeGen/X86/twoaddr-lea.ll (original) +++ llvm/branches/release_39/test/CodeGen/X86/twoaddr-lea.ll Tue Aug 9 10:48:01 2016 @@ -44,3 +44,60 @@ entry: %0 = shl i64 %x, 1 ret i64 %0 } + +@global = external global i32, align 4 +@global2 = external global i64, align 8 + +; Test that liveness is properly updated and we do not encounter the +; assert/crash from http://llvm.org/PR28301 +; CHECK-LABEL: ham +define void @ham() { +bb: + br label %bb1 + +bb1: + %tmp = phi i64 [ %tmp40, %bb9 ], [ 0, %bb ] + %tmp2 = phi i32 [ %tmp39, %bb9 ], [ 0, %bb ] + %tmp3 = icmp sgt i32 undef, 10 + br i1 %tmp3, label %bb2, label %bb3 + +bb2: + %tmp6 = load i32, i32* @global, align 4 + %tmp8 = add nsw i32 %tmp6, %tmp2 + %tmp9 = sext i32 %tmp8 to i64 + br label %bb6 + +bb3: +; CHECK: subl %e[[REG0:[a-z0-9]+]], +; CHECK: leaq 4({{%[a-z0-9]+}}), %r[[REG0]] + %tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ] + %tmp15 = add nuw i64 %tmp14, 4 + %tmp16 = trunc i64 %tmp14 to i32 + %tmp17 = sub i32 %tmp2, %tmp16 + br label %bb4 + +bb4: + %tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ] + %tmp28 = icmp eq i32 %tmp17, 0 + br i1 %tmp28, label %bb5, label %bb8 + +bb5: + %tmp34 = add nuw nsw i64 %tmp20, 1 + %tmp35 = icmp slt i64 %tmp34, %tmp15 + br i1 %tmp35, label %bb4, label %bb3 + +bb6: + store volatile i64 %tmp, i64* @global2, align 8 + store volatile i64 %tmp9, i64* @global2, align 8 + store volatile i32 %tmp6, i32* @global, align 4 + %tmp45 = icmp slt i32 undef, undef + br i1 %tmp45, label %bb6, label %bb9 + +bb8: + unreachable + +bb9: + %tmp39 = add nuw nsw i32 %tmp2, 4 + %tmp40 = add nuw i64 %tmp, 4 + br label %bb1 +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
