Author: mohit.bhakkad
Date: Wed May 25 01:30:52 2016
New Revision: 270675
URL: http://llvm.org/viewvc/llvm-project?rev=270675&view=rev
Log:
Merging r265134:
------------------------------------------------------------------------
r265134 | slthakur | 2016-04-01 17:25:33 +0530 (Fri, 01 Apr 2016) | 9 lines
[MIPS][LLVM-MC] Fix JR encoding for MIPSR6 ISA
Summary: The assembler was picking the wrong JR variant because the pre-R6 one
was still enabled at R6.
Author: nitesh.jain
Reviewers: vkalintiris, dsanders
Subscribers: dsanders, llvm-commits, mohit.bhakkad, sagar, bhushan, jaydeep
Differential: D18387
------------------------------------------------------------------------
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/Mips/MipsInstrInfo.td
llvm/branches/release_38/test/MC/Mips/mips32r6/valid.s
llvm/branches/release_38/test/MC/Mips/mips64r6/valid.s
Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Wed May 25 01:30:52 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365,261368,261384,261387,261441,261447,261546,264335,267634
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365,261368,261384,261387,261441,261447,261546,264335,265134,267634
Modified: llvm/branches/release_38/lib/Target/Mips/MipsInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/Mips/MipsInstrInfo.td?rev=270675&r1=270674&r2=270675&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/branches/release_38/lib/Target/Mips/MipsInstrInfo.td Wed May 25
01:30:52 2016
@@ -1507,7 +1507,7 @@ def SC : SCBase<"sc", GPR32Opnd>, LW_FM<
/// Jump and Branch Instructions
def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
AdditionalRequires<[RelocStatic]>, IsBranch;
-def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
+def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>,
ISA_MIPS1_NOT_32R6_64R6;
def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
Modified: llvm/branches/release_38/test/MC/Mips/mips32r6/valid.s
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/MC/Mips/mips32r6/valid.s?rev=270675&r1=270674&r2=270675&view=diff
==============================================================================
--- llvm/branches/release_38/test/MC/Mips/mips32r6/valid.s (original)
+++ llvm/branches/release_38/test/MC/Mips/mips32r6/valid.s Wed May 25 01:30:52
2016
@@ -161,6 +161,8 @@ a:
j 1328 # CHECK: j 1328 # encoding:
[0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding:
[0x0c,0x00,0x14,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding:
[0x00,0x80,0x04,0x09]
+ jr $ra # CHECK: jr $ra # encoding:
[0x03,0xe0,0x00,0x09]
+ jr $25 # CHECK: jr $25 # encoding:
[0x03,0x20,0x00,0x09]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding:
[0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding:
[0x00,0xa0,0x24,0x09]
ldc2 $8, -701($at) # CHECK: ldc2 $8, -701($1) # encoding:
[0x49,0xc8,0x0d,0x43]
Modified: llvm/branches/release_38/test/MC/Mips/mips64r6/valid.s
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/MC/Mips/mips64r6/valid.s?rev=270675&r1=270674&r2=270675&view=diff
==============================================================================
--- llvm/branches/release_38/test/MC/Mips/mips64r6/valid.s (original)
+++ llvm/branches/release_38/test/MC/Mips/mips64r6/valid.s Wed May 25 01:30:52
2016
@@ -140,6 +140,8 @@ a:
j 1328 # CHECK: j 1328 # encoding:
[0x08,0x00,0x01,0x4c]
jal 21100 # CHECK: jal 21100 # encoding:
[0x0c,0x00,0x14,0x9b]
jr.hb $4 # CHECK: jr.hb $4 # encoding:
[0x00,0x80,0x04,0x09]
+ jr $ra # CHECK: jr $ra # encoding:
[0x03,0xe0,0x00,0x09]
+ jr $25 # CHECK: jr $25 # encoding:
[0x03,0x20,0x00,0x09]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding:
[0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding:
[0x00,0xa0,0x24,0x09]
jialc $5, 256 # CHECK: jialc $5, 256 # encoding:
[0xf8,0x05,0x01,0x00]
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