Author: hans
Date: Mon Feb 22 12:48:10 2016
New Revision: 261553
URL: http://llvm.org/viewvc/llvm-project?rev=261553&view=rev
Log:
Merging r261422:
------------------------------------------------------------------------
r261422 | rdivacky | 2016-02-20 00:31:24 -0800 (Sat, 20 Feb 2016) | 10 lines
Fix handling of vaargs on PPC32 when going from regsave to overflow.
It can happen that when we only have 1 more register left in the regsave
area we need to store a value bigger than 1 register and therefore we
go to the overflow area. In this case we have to leave the last slot
in the regsave area unused and keep using overflow area. Do this
by storing a limit value to the used register counter in the overflow block.
Issue diagnosed by and solution tested by Mark Millard!
------------------------------------------------------------------------
Modified:
cfe/branches/release_38/ (props changed)
cfe/branches/release_38/lib/CodeGen/TargetInfo.cpp
cfe/branches/release_38/test/CodeGen/ppc-varargs-struct.c
Propchange: cfe/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Feb 22 12:48:10 2016
@@ -1,4 +1,4 @@
/cfe/branches/type-system-rewrite:134693-134817
-/cfe/trunk:257652,257695,257710,257763,257831,257838,257853,257861,257869-257871,257947,258110,258396,259183,259260,259598,259874,259931,260370,260616,260637,260851,261080,261209
+/cfe/trunk:257652,257695,257710,257763,257831,257838,257853,257861,257869-257871,257947,258110,258396,259183,259260,259598,259874,259931,260370,260616,260637,260851,261080,261209,261309,261422
/cfe/trunk/test:170344
/cfe/trunk/test/SemaTemplate:126920
Modified: cfe/branches/release_38/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_38/lib/CodeGen/TargetInfo.cpp?rev=261553&r1=261552&r2=261553&view=diff
==============================================================================
--- cfe/branches/release_38/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/branches/release_38/lib/CodeGen/TargetInfo.cpp Mon Feb 22 12:48:10 2016
@@ -3475,6 +3475,7 @@ public:
Address PPC32_SVR4_ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAList,
QualType Ty) const {
+ const unsigned OverflowLimit = 8;
if (const ComplexType *CTy = Ty->getAs<ComplexType>()) {
// TODO: Implement this. For now ignore.
(void)CTy;
@@ -3517,7 +3518,7 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
}
llvm::Value *CC =
- Builder.CreateICmpULT(NumRegs, Builder.getInt8(8), "cond");
+ Builder.CreateICmpULT(NumRegs, Builder.getInt8(OverflowLimit), "cond");
llvm::BasicBlock *UsingRegs = CGF.createBasicBlock("using_regs");
llvm::BasicBlock *UsingOverflow = CGF.createBasicBlock("using_overflow");
@@ -3569,6 +3570,8 @@ Address PPC32_SVR4_ABIInfo::EmitVAArg(Co
{
CGF.EmitBlock(UsingOverflow);
+ Builder.CreateStore(Builder.getInt8(OverflowLimit), NumRegsAddr);
+
// Everything in the overflow area is rounded up to a size of at least 4.
CharUnits OverflowAreaAlign = CharUnits::fromQuantity(4);
Modified: cfe/branches/release_38/test/CodeGen/ppc-varargs-struct.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/branches/release_38/test/CodeGen/ppc-varargs-struct.c?rev=261553&r1=261552&r2=261553&view=diff
==============================================================================
--- cfe/branches/release_38/test/CodeGen/ppc-varargs-struct.c (original)
+++ cfe/branches/release_38/test/CodeGen/ppc-varargs-struct.c Mon Feb 22
12:48:10 2016
@@ -37,6 +37,7 @@ void testva (int n, ...)
// CHECK-PPC-NEXT: br label %[[CONT:[a-z0-9]+]]
//
// CHECK-PPC:[[USING_OVERFLOW]]
+// CHECK-PPC-NEXT: store i8 8, i8* [[GPRPTR]], align 4
// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds
%struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3
// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8**
[[OVERFLOW_AREA_P]], align 4
// CHECK-PPC-NEXT: %{{[0-9]+}} = ptrtoint i8* %argp.cur to i32
@@ -76,6 +77,7 @@ void testva (int n, ...)
// CHECK-PPC-NEXT: br label %[[CONT:[a-z0-9]+]]
//
// CHECK-PPC:[[USING_OVERFLOW]]
+// CHECK-PPC-NEXT: store i8 8, i8* [[GPRPTR]], align 4
// CHECK-PPC-NEXT: [[OVERFLOW_AREA_P:%[0-9]+]] = getelementptr inbounds
%struct.__va_list_tag, %struct.__va_list_tag* [[ARRAYDECAY]], i32 0, i32 3
// CHECK-PPC-NEXT: [[OVERFLOW_AREA:%.+]] = load i8*, i8**
[[OVERFLOW_AREA_P]], align 4
// CHECK-PPC-NEXT: [[MEMADDR:%.+]] = bitcast i8* [[OVERFLOW_AREA]] to i32*
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