Author: hans
Date: Mon Feb 22 11:47:10 2016
New Revision: 261539
URL: http://llvm.org/viewvc/llvm-project?rev=261539&view=rev
Log:
Merging r261384:
------------------------------------------------------------------------
r261384 | qcolombet | 2016-02-19 16:32:29 -0800 (Fri, 19 Feb 2016) | 4 lines
[RegAllocFast] Properly track the physical register definitions on calls.
PR26485
------------------------------------------------------------------------
Added:
llvm/branches/release_38/test/CodeGen/X86/i386-tlscall-fastregalloc.ll
- copied unchanged from r261384,
llvm/trunk/test/CodeGen/X86/i386-tlscall-fastregalloc.ll
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/CodeGen/RegAllocFast.cpp
llvm/branches/release_38/test/CodeGen/ARM/Windows/alloca.ll
Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Mon Feb 22 11:47:10 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365,261368
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257864,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258103,258112,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258609-258611,258616,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259381,259645,259649,259695-259696,259702,259740,259798,259835,259840,259886,259888,259958,260164,260390,260427,260587,260641,260703,260733,261033,261039,261258,261306,261360,261365,261368,261384
Modified: llvm/branches/release_38/lib/CodeGen/RegAllocFast.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/CodeGen/RegAllocFast.cpp?rev=261539&r1=261538&r2=261539&view=diff
==============================================================================
--- llvm/branches/release_38/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/branches/release_38/lib/CodeGen/RegAllocFast.cpp Mon Feb 22 11:47:10
2016
@@ -1002,11 +1002,13 @@ void RAFast::AllocateBasicBlock() {
unsigned DefOpEnd = MI->getNumOperands();
if (MI->isCall()) {
- // Spill all virtregs before a call. This serves two purposes: 1. If an
+ // Spill all virtregs before a call. This serves one purpose: If an
// exception is thrown, the landing pad is going to expect to find
- // registers in their spill slots, and 2. we don't have to wade through
- // all the <imp-def> operands on the call instruction.
- DefOpEnd = VirtOpEnd;
+ // registers in their spill slots.
+ // Note: although this is appealing to just consider all definitions
+ // as call-clobbered, this is not correct because some of those
+ // definitions may be used later on and we do not want to reuse
+ // those for virtual registers in between.
DEBUG(dbgs() << " Spilling remaining registers before call.\n");
spillAll(MI);
Modified: llvm/branches/release_38/test/CodeGen/ARM/Windows/alloca.ll
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/ARM/Windows/alloca.ll?rev=261539&r1=261538&r2=261539&view=diff
==============================================================================
--- llvm/branches/release_38/test/CodeGen/ARM/Windows/alloca.ll (original)
+++ llvm/branches/release_38/test/CodeGen/ARM/Windows/alloca.ll Mon Feb 22
11:47:10 2016
@@ -13,7 +13,9 @@ entry:
}
; CHECK: bl num_entries
-; CHECK: movs [[R1:r[0-9]+]], #7
+; Any register is actually valid here, but turns out we use lr,
+; because we do not have the kill flag on R0.
+; CHECK: mov.w [[R1:lr]], #7
; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
; CHECK: bic [[R0]], [[R0]], #7
; CHECK: lsrs r4, [[R0]], #2
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