Author: hans
Date: Thu Feb 4 18:55:39 2016
New Revision: 259858
URL: http://llvm.org/viewvc/llvm-project?rev=259858&view=rev
Log:
Merging r259840 on top of r259178:
------------------------------------------------------------------------
r259178 | echristo | 2016-01-28 23:20:30 -0800 (Thu, 28 Jan 2016) | 1 line
Refactor common code for PPC fast isel load immediate selection.
------------------------------------------------------------------------
------------------------------------------------------------------------
r259840 | nemanjai | 2016-02-04 15:14:42 -0800 (Thu, 04 Feb 2016) | 7 lines
Fix for PR 26356
Using the load immediate only when the immediate (whether signed or unsigned)
can fit in a 16-bit signed field. Namely, from -32768 to 32767 for signed and
0 to 65535 for unsigned. This patch also ensures that we sign-extend under the
right conditions.
------------------------------------------------------------------------
Added:
llvm/branches/release_38/test/CodeGen/PowerPC/pr26356.ll
- copied unchanged from r259840,
llvm/trunk/test/CodeGen/PowerPC/pr26356.ll
Modified:
llvm/branches/release_38/ (props changed)
llvm/branches/release_38/lib/Target/PowerPC/PPCFastISel.cpp
Propchange: llvm/branches/release_38/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Thu Feb 4 18:55:39 2016
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259177,259228,259236,259342,259346,259375,259645,259649,259695,259740,259798,259835
+/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891,258971,259177-259178,259228,259236,259342,259346,259375,259645,259649,259695,259740,259798,259835,259840
Modified: llvm/branches/release_38/lib/Target/PowerPC/PPCFastISel.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/PowerPC/PPCFastISel.cpp?rev=259858&r1=259857&r2=259858&view=diff
==============================================================================
--- llvm/branches/release_38/lib/Target/PowerPC/PPCFastISel.cpp (original)
+++ llvm/branches/release_38/lib/Target/PowerPC/PPCFastISel.cpp Thu Feb 4
18:55:39 2016
@@ -1615,7 +1615,7 @@ bool PPCFastISel::SelectRet(const Instru
// extension rather than sign extension. Make sure we pass the return
// value extension property to integer materialization.
unsigned SrcReg =
- PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() ==
CCValAssign::SExt);
+ PPCMaterializeInt(CI, MVT::i64, VA.getLocInfo() !=
CCValAssign::ZExt);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
@@ -2091,26 +2091,21 @@ unsigned PPCFastISel::PPCMaterializeInt(
const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
&PPC::GPRCRegClass);
+ int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
// If the constant is in range, use a load-immediate.
- if (UseSExt && isInt<16>(CI->getSExtValue())) {
- unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
- unsigned ImmReg = createResultReg(RC);
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
- .addImm(CI->getSExtValue());
- return ImmReg;
- } else if (!UseSExt && isUInt<16>(CI->getSExtValue())) {
- // Since LI will sign extend the constant we need to make sure that for
- // our zeroext constants that the sign extended constant fits into 16-bits.
+ // Since LI will sign extend the constant we need to make sure that for
+ // our zeroext constants that the sign extended constant fits into 16-bits -
+ // a range of 0..0x7fff.
+ if (isInt<16>(Imm)) {
unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
unsigned ImmReg = createResultReg(RC);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
- .addImm(CI->getZExtValue());
+ .addImm(Imm);
return ImmReg;
}
// Construct the constant piecewise.
- int64_t Imm = UseSExt ? CI->getSExtValue() : CI->getZExtValue();
if (VT == MVT::i64)
return PPCMaterialize64BitInt(Imm, RC);
else if (VT == MVT::i32)
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