Author: hans Date: Thu Jan 28 12:16:55 2016 New Revision: 259064 URL: http://llvm.org/viewvc/llvm-project?rev=259064&view=rev Log: Merging r258471: ------------------------------------------------------------------------ r258471 | pirama | 2016-01-21 17:16:57 -0800 (Thu, 21 Jan 2016) | 14 lines
Do not lower VSETCC if operand is an f16 vector Summary: SETCC with f16 vectors has OperationAction set to Expand but still gets lowered to FCM* intrinsics based on its result type. This patch skips lowering of VSETCC if the operand is an f16 vector. v4 and v8 tests included. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15361 ------------------------------------------------------------------------ Modified: llvm/branches/release_38/ (props changed) llvm/branches/release_38/lib/Target/AArch64/AArch64ISelLowering.cpp llvm/branches/release_38/test/CodeGen/AArch64/fp16-v4-instructions.ll llvm/branches/release_38/test/CodeGen/AArch64/fp16-v8-instructions.ll Propchange: llvm/branches/release_38/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Jan 28 12:16:55 2016 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258690,258729,258891 +/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258184,258207,258221,258273,258325,258406,258416,258428,258436,258471,258690,258729,258891 Modified: llvm/branches/release_38/lib/Target/AArch64/AArch64ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=259064&r1=259063&r2=259064&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/AArch64/AArch64ISelLowering.cpp (original) +++ llvm/branches/release_38/lib/Target/AArch64/AArch64ISelLowering.cpp Thu Jan 28 12:16:55 2016 @@ -6689,6 +6689,9 @@ SDValue AArch64TargetLowering::LowerVSET return DAG.getSExtOrTrunc(Cmp, dl, Op.getValueType()); } + if (LHS.getValueType().getVectorElementType() == MVT::f16) + return SDValue(); + assert(LHS.getValueType().getVectorElementType() == MVT::f32 || LHS.getValueType().getVectorElementType() == MVT::f64); Modified: llvm/branches/release_38/test/CodeGen/AArch64/fp16-v4-instructions.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AArch64/fp16-v4-instructions.ll?rev=259064&r1=259063&r2=259064&view=diff ============================================================================== --- llvm/branches/release_38/test/CodeGen/AArch64/fp16-v4-instructions.ll (original) +++ llvm/branches/release_38/test/CodeGen/AArch64/fp16-v4-instructions.ll Thu Jan 28 12:16:55 2016 @@ -267,4 +267,278 @@ define <4 x i16> @fptoui_i16(<4 x half> ret <4 x i16> %1 } +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_une: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, ne +; CHECK-DAG: csel {{.*}}, wzr, ne +; CHECK-DAG: csel {{.*}}, wzr, ne +; CHECK-DAG: csel {{.*}}, wzr, ne +define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp une <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ueq: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, vs +; CHECK-DAG: csel {{.*}}, vs +; CHECK-DAG: csel {{.*}}, vs +; CHECK-DAG: csel {{.*}}, vs +define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ueq <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ugt: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, hi +; CHECK-DAG: csel {{.*}}, wzr, hi +; CHECK-DAG: csel {{.*}}, wzr, hi +; CHECK-DAG: csel {{.*}}, wzr, hi +define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ugt <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_uge: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, pl +; CHECK-DAG: csel {{.*}}, wzr, pl +; CHECK-DAG: csel {{.*}}, wzr, pl +; CHECK-DAG: csel {{.*}}, wzr, pl +define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp uge <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ult: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, lt +; CHECK-DAG: csel {{.*}}, wzr, lt +; CHECK-DAG: csel {{.*}}, wzr, lt +; CHECK-DAG: csel {{.*}}, wzr, lt +define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ult <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ule: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, le +; CHECK-DAG: csel {{.*}}, wzr, le +; CHECK-DAG: csel {{.*}}, wzr, le +; CHECK-DAG: csel {{.*}}, wzr, le +define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ule <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_uno: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, vs +; CHECK-DAG: csel {{.*}}, wzr, vs +; CHECK-DAG: csel {{.*}}, wzr, vs +; CHECK-DAG: csel {{.*}}, wzr, vs +define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp uno <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_one: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, gt +; CHECK-DAG: csel {{.*}}, gt +; CHECK-DAG: csel {{.*}}, gt +; CHECK-DAG: csel {{.*}}, gt +define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp one <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_oeq: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csel {{.*}}, wzr, eq +define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp oeq <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ogt: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, gt +; CHECK-DAG: csel {{.*}}, wzr, gt +; CHECK-DAG: csel {{.*}}, wzr, gt +; CHECK-DAG: csel {{.*}}, wzr, gt +define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ogt <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_oge: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, ge +; CHECK-DAG: csel {{.*}}, wzr, ge +; CHECK-DAG: csel {{.*}}, wzr, ge +; CHECK-DAG: csel {{.*}}, wzr, ge +define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp oge <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_olt: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csel {{.*}}, wzr, mi +define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp olt <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ole: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, ls +; CHECK-DAG: csel {{.*}}, wzr, ls +; CHECK-DAG: csel {{.*}}, wzr, ls +; CHECK-DAG: csel {{.*}}, wzr, ls +define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ole <4 x half> %a, %b + ret <4 x i1> %1 +} + +; Function Attrs: nounwind readnone +; CHECK-LABEL: test_fcmp_ord: +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: fcvt +; CHECK-DAG: csel {{.*}}, wzr, vc +; CHECK-DAG: csel {{.*}}, wzr, vc +; CHECK-DAG: csel {{.*}}, wzr, vc +; CHECK-DAG: csel {{.*}}, wzr, vc +define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 { + %1 = fcmp ord <4 x half> %a, %b + ret <4 x i1> %1 +} + attributes #0 = { nounwind } Modified: llvm/branches/release_38/test/CodeGen/AArch64/fp16-v8-instructions.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/AArch64/fp16-v8-instructions.ll?rev=259064&r1=259063&r2=259064&view=diff ============================================================================== --- llvm/branches/release_38/test/CodeGen/AArch64/fp16-v8-instructions.ll (original) +++ llvm/branches/release_38/test/CodeGen/AArch64/fp16-v8-instructions.ll Thu Jan 28 12:16:55 2016 @@ -421,4 +421,88 @@ define <8 x i16> @fptoui_i16(<8 x half> ret <8 x i16> %1 } +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp une <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 16 csel tests. Skipped. +define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ueq <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ugt <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp uge <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ult <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ule <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp uno <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp one <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp oeq <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ogt <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp oge <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp olt <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ole <8 x half> %a, %b + ret <8 x i1> %1 +} + +; FileCheck checks are unwieldy with 16 fcvt and 8 csel tests. Skipped. +define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 { + %1 = fcmp ord <8 x half> %a, %b + ret <8 x i1> %1 +} + attributes #0 = { nounwind } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
