Author: hans Date: Tue Jan 26 13:31:16 2016 New Revision: 258840 URL: http://llvm.org/viewvc/llvm-project?rev=258840&view=rev Log: Merging r258729: ------------------------------------------------------------------------ r258729 | matze | 2016-01-25 14:08:25 -0800 (Mon, 25 Jan 2016) | 13 lines
X86ISelLowering: Fix cmov(cmov) special lowering bug There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) ------------------------------------------------------------------------ Modified: llvm/branches/release_38/ (props changed) llvm/branches/release_38/lib/Target/X86/X86ISelLowering.cpp llvm/branches/release_38/test/CodeGen/X86/cmovcmov.ll Propchange: llvm/branches/release_38/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Tue Jan 26 13:31:16 2016 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258207,258221,258273,258325,258406,258416,258428,258690 +/llvm/trunk:155241,257645,257648,257730,257775,257791,257875,257886,257902,257905,257925,257929-257930,257940,257942,257977,257979,257997,258168,258207,258221,258273,258325,258406,258416,258428,258690,258729 Modified: llvm/branches/release_38/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/lib/Target/X86/X86ISelLowering.cpp?rev=258840&r1=258839&r2=258840&view=diff ============================================================================== --- llvm/branches/release_38/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/branches/release_38/lib/Target/X86/X86ISelLowering.cpp Tue Jan 26 13:31:16 2016 @@ -21880,7 +21880,8 @@ X86TargetLowering::EmitLoweredSelect(Mac if (LastCMOV == MI && NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() && NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() && - NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) { + NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg() && + NextMIIt->getOperand(1).isKill()) { CascadedCMOV = &*NextMIIt; } Modified: llvm/branches/release_38/test/CodeGen/X86/cmovcmov.ll URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_38/test/CodeGen/X86/cmovcmov.ll?rev=258840&r1=258839&r2=258840&view=diff ============================================================================== --- llvm/branches/release_38/test/CodeGen/X86/cmovcmov.ll (original) +++ llvm/branches/release_38/test/CodeGen/X86/cmovcmov.ll Tue Jan 26 13:31:16 2016 @@ -224,3 +224,52 @@ entry: } attributes #0 = { nounwind } + +@g8 = global i8 0 + +; The following test failed because llvm had a bug where a structure like: +; +; %vreg12<def> = CMOV_GR8 %vreg7, %vreg11 ... (lt) +; %vreg13<def> = CMOV_GR8 %vreg12, %vreg11 ... (gt) +; +; was lowered to: +; +; The first two cmovs got expanded to: +; BB#0: +; JL_1 BB#9 +; BB#7: +; JG_1 BB#9 +; BB#8: +; BB#9: +; vreg12 = phi(vreg7, BB#8, vreg11, BB#0, vreg12, BB#7) +; vreg13 = COPY vreg12 +; Which was invalid as %vreg12 is not the same value as %vreg13 + +; CHECK-LABEL: no_cascade_opt: +; CMOV-DAG: cmpl %edx, %esi +; CMOV-DAG: movb $20, %al +; CMOV-DAG: movb $20, %dl +; CMOV: jl [[BB0:.LBB[0-9_]+]] +; CMOV: movb %cl, %dl +; CMOV: [[BB0]]: +; CMOV: jg [[BB1:.LBB[0-9_]+]] +; CMOV: movb %dl, %al +; CMOV: [[BB1]]: +; CMOV: testl %edi, %edi +; CMOV: je [[BB2:.LBB[0-9_]+]] +; CMOV: movb %dl, %al +; CMOV: [[BB2]]: +; CMOV: movb %al, g8(%rip) +; CMOV: retq +define void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) { +entry: + %c0 = icmp eq i32 %v0, 0 + %c1 = icmp slt i32 %v1, %v2 + %c2 = icmp sgt i32 %v1, %v2 + %trunc = trunc i32 %v3 to i8 + %sel0 = select i1 %c1, i8 20, i8 %trunc + %sel1 = select i1 %c2, i8 20, i8 %sel0 + %sel2 = select i1 %c0, i8 %sel1, i8 %sel0 + store volatile i8 %sel2, i8* @g8 + ret void +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
