Author: ast
Date: Fri Oct 23 20:58:14 2015
New Revision: 251175
URL: http://llvm.org/viewvc/llvm-project?rev=251175&view=rev
Log:
Merging r249371:
------------------------------------------------------------------------
r249371 | ast | 2015-10-05 21:00:53 -0700 (Mon, 05 Oct 2015) | 25 lines
[bpf] Avoid extra pointer arithmetic for stack access
For the program like below
struct key_t {
int pid;
char name[16];
};
extern void test1(char *);
int test() {
struct key_t key = {};
test1(key.name);
return 0;
}
For key.name, the llc/bpf may generate the below code:
R1 = R10 // R10 is the frame pointer
R1 += -24 // framepointer adjustment
R1 |= 4 // R1 is then used as the first parameter of test1
OR operation is not recognized by in-kernel verifier.
This patch introduces an intermediate FI_ri instruction and
generates the following code that can be properly verified:
R1 = R10
R1 += -20
Patch by Yonghong Song <y...@plumgrid.com>
------------------------------------------------------------------------
Added:
llvm/branches/release_37/test/CodeGen/BPF/fi_ri.ll
- copied unchanged from r249371, llvm/trunk/test/CodeGen/BPF/fi_ri.ll
Modified:
llvm/branches/release_37/ (props changed)
llvm/branches/release_37/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/branches/release_37/lib/Target/BPF/BPFInstrInfo.td
llvm/branches/release_37/lib/Target/BPF/BPFRegisterInfo.cpp
Propchange: llvm/branches/release_37/
------------------------------------------------------------------------------
--- svn:mergeinfo (original)
+++ svn:mergeinfo Fri Oct 23 20:58:14 2015
@@ -1,3 +1,3 @@
/llvm/branches/Apple/Pertwee:110850,110961
/llvm/branches/type-system-rewrite:133420-134817
-/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,244448,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902,247372,247951
+/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,244448,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902,247372,247951,249371
Modified: llvm/branches/release_37/lib/Target/BPF/BPFISelDAGToDAG.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/BPF/BPFISelDAGToDAG.cpp?rev=251175&r1=251174&r2=251175&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/BPF/BPFISelDAGToDAG.cpp (original)
+++ llvm/branches/release_37/lib/Target/BPF/BPFISelDAGToDAG.cpp Fri Oct 23
20:58:14 2015
@@ -50,6 +50,7 @@ private:
// Complex Pattern for address selection.
bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
+ bool SelectFIAddr(SDValue Addr, SDValue &Base, SDValue &Offset);
};
}
@@ -67,7 +68,7 @@ bool BPFDAGToDAGISel::SelectAddr(SDValue
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false;
- // Addresses of the form FI+const or FI|const
+ // Addresses of the form Addr+const or Addr|const
if (CurDAG->isBaseWithConstantOffset(Addr)) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
if (isInt<32>(CN->getSExtValue())) {
@@ -89,6 +90,31 @@ bool BPFDAGToDAGISel::SelectAddr(SDValue
return true;
}
+// ComplexPattern used on BPF FI instruction
+bool BPFDAGToDAGISel::SelectFIAddr(SDValue Addr, SDValue &Base, SDValue
&Offset) {
+ SDLoc DL(Addr);
+
+ if (!CurDAG->isBaseWithConstantOffset(Addr))
+ return false;
+
+ // Addresses of the form Addr+const or Addr|const
+ ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+ if (isInt<32>(CN->getSExtValue())) {
+
+ // If the first operand is a FI, get the TargetFI Node
+ if (FrameIndexSDNode *FIN =
+ dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
+ Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
+ else
+ return false;
+
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64);
+ return true;
+ }
+
+ return false;
+}
+
SDNode *BPFDAGToDAGISel::Select(SDNode *Node) {
unsigned Opcode = Node->getOpcode();
Modified: llvm/branches/release_37/lib/Target/BPF/BPFInstrInfo.td
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/BPF/BPFInstrInfo.td?rev=251175&r1=251174&r2=251175&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/BPF/BPFInstrInfo.td (original)
+++ llvm/branches/release_37/lib/Target/BPF/BPFInstrInfo.td Fri Oct 23 20:58:14
2015
@@ -54,7 +54,8 @@ def i64immSExt32 : PatLeaf<(imm),
[{return isInt<32>(N->getSExtValue()); }]>;
// Addressing modes.
-def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [frameindex], []>;
+def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>;
+def FIri : ComplexPattern<i64, 2, "SelectFIAddr", [add, or], []>;
// Address operands
def MEMri : Operand<i64> {
@@ -260,6 +261,15 @@ def MOV_rr : MOV_RR<"mov">;
def MOV_ri : MOV_RI<"mov">;
}
+def FI_ri
+ : InstBPF<(outs GPR:$dst), (ins MEMri:$addr),
+ "lea\t$dst, $addr",
+ [(set i64:$dst, FIri:$addr)]> {
+ // This is a tentative instruction, and will be replaced
+ // with MOV_rr and ADD_ri in PEI phase
+}
+
+
def LD_pseudo
: InstBPF<(outs GPR:$dst), (ins i64imm:$pseudo, u64imm:$imm),
"ld_pseudo\t$dst, $pseudo, $imm",
Modified: llvm/branches/release_37/lib/Target/BPF/BPFRegisterInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/BPF/BPFRegisterInfo.cpp?rev=251175&r1=251174&r2=251175&view=diff
==============================================================================
--- llvm/branches/release_37/lib/Target/BPF/BPFRegisterInfo.cpp (original)
+++ llvm/branches/release_37/lib/Target/BPF/BPFRegisterInfo.cpp Fri Oct 23
20:58:14 2015
@@ -58,14 +58,13 @@ void BPFRegisterInfo::eliminateFrameInde
unsigned FrameReg = getFrameRegister(MF);
int FrameIndex = MI.getOperand(i).getIndex();
+ const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
+ MachineBasicBlock &MBB = *MI.getParent();
if (MI.getOpcode() == BPF::MOV_rr) {
- const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
MI.getOperand(i).ChangeToRegister(FrameReg, false);
-
- MachineBasicBlock &MBB = *MI.getParent();
unsigned reg = MI.getOperand(i - 1).getReg();
BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
.addReg(reg)
@@ -79,8 +78,24 @@ void BPFRegisterInfo::eliminateFrameInde
if (!isInt<32>(Offset))
llvm_unreachable("bug in frame offset");
- MI.getOperand(i).ChangeToRegister(FrameReg, false);
- MI.getOperand(i + 1).ChangeToImmediate(Offset);
+ if (MI.getOpcode() == BPF::FI_ri) {
+ // architecture does not really support FI_ri, replace it with
+ // MOV_rr <target_reg>, frame_reg
+ // ADD_ri <target_reg>, imm
+ unsigned reg = MI.getOperand(i - 1).getReg();
+
+ BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
+ .addReg(FrameReg);
+ BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
+ .addReg(reg)
+ .addImm(Offset);
+
+ // Remove FI_ri instruction
+ MI.eraseFromParent();
+ } else {
+ MI.getOperand(i).ChangeToRegister(FrameReg, false);
+ MI.getOperand(i + 1).ChangeToImmediate(Offset);
+ }
}
unsigned BPFRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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