Author: dsanders Date: Thu Nov 5 07:30:33 2015 New Revision: 252158 URL: http://llvm.org/viewvc/llvm-project?rev=252158&view=rev Log: Merging r251622: ------------------------------------------------------------------------ r251622 | vkalintiris | 2015-10-29 10:17:16 +0000 (Thu, 29 Oct 2015) | 17 lines
[mips] Check the register class before replacing materializations of zero with $zero in microMIPS. Summary: The microMIPS register class GPRMM16 does not contain the $zero register. However, MipsSEDAGToDAGISel::replaceUsesWithZeroReg() would replace uses of the $dst register: [d]addiu, $dst, $zero, 0 with the $zero register, without checking for membership in the register class of the target machine operand. Reviewers: dsanders Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13984 ------------------------------------------------------------------------ Added: llvm/branches/release_37/test/CodeGen/Mips/micromips-zero-mat-uses.ll - copied unchanged from r251622, llvm/trunk/test/CodeGen/Mips/micromips-zero-mat-uses.ll Modified: llvm/branches/release_37/ (props changed) llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Propchange: llvm/branches/release_37/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Thu Nov 5 07:30:33 2015 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,244448,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902,247372,247951,249371,249718 +/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242372,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244232,244332,244418,244448,244554,244644,244659,244676,244789,244889,245064,245105,245119,245256,245355,245365,245369,245394-245395,245530,245535,245902,247372,247951,249371,249718,251622 Modified: llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp?rev=252158&r1=252157&r2=252158&view=diff ============================================================================== --- llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (original) +++ llvm/branches/release_37/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Thu Nov 5 07:30:33 2015 @@ -115,6 +115,11 @@ bool MipsSEDAGToDAGISel::replaceUsesWith if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo()) continue; + // Also, we have to check that the register class of the operand + // contains the zero register. + if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) + continue; + MO.setReg(ZeroReg); } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
