Author: hans Date: Fri Aug 14 13:34:33 2015 New Revision: 245080 URL: http://llvm.org/viewvc/llvm-project?rev=245080&view=rev Log: Merging r244332: ------------------------------------------------------------------------ r244332 | tstellar | 2015-08-07 09:45:33 -0700 (Fri, 07 Aug 2015) | 9 lines
AMDGPU/SI: Use correct encoding of vopc for VI in the assembler Summary: We were using the SI encoding for VI. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11812 ------------------------------------------------------------------------ Modified: llvm/branches/release_37/ (props changed) llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.td llvm/branches/release_37/test/MC/AMDGPU/vopc.s Propchange: llvm/branches/release_37/ ------------------------------------------------------------------------------ --- svn:mergeinfo (original) +++ svn:mergeinfo Fri Aug 14 13:34:33 2015 @@ -1,3 +1,3 @@ /llvm/branches/Apple/Pertwee:110850,110961 /llvm/branches/type-system-rewrite:133420-134817 -/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244418,244554,244644,244676,244789,244889 +/llvm/trunk:155241,242236,242239,242281,242288,242296,242331,242341,242410,242412,242433-242434,242442,242543,242673,242680,242706,242721-242722,242733-242735,242742,242869,242919,242993,243001,243057,243116,243263,243294,243361,243469,243485,243500,243519,243531,243589,243609,243636,243638-243640,243745,243891,243898,243927,243932,243934,243984,243986,243999,244058,244123,244332,244418,244554,244644,244676,244789,244889 Modified: llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.td?rev=245080&r1=245079&r2=245080&view=diff ============================================================================== --- llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.td (original) +++ llvm/branches/release_37/lib/Target/AMDGPU/SIInstrInfo.td Fri Aug 14 13:34:33 2015 @@ -1600,12 +1600,14 @@ multiclass VOPC_m <vopc op, dag outs, da SIMCInstr <opName#"_e32", SISubtarget.SI> { let Defs = !if(DefExec, [EXEC], []); let hasSideEffects = DefExec; + let AssemblerPredicates = [isSICI]; } def _vi : VOPC<op.VI, ins, asm, []>, SIMCInstr <opName#"_e32", SISubtarget.VI> { let Defs = !if(DefExec, [EXEC], []); let hasSideEffects = DefExec; + let AssemblerPredicates = [isVI]; } } Modified: llvm/branches/release_37/test/MC/AMDGPU/vopc.s URL: http://llvm.org/viewvc/llvm-project/llvm/branches/release_37/test/MC/AMDGPU/vopc.s?rev=245080&r1=245079&r2=245080&view=diff ============================================================================== --- llvm/branches/release_37/test/MC/AMDGPU/vopc.s (original) +++ llvm/branches/release_37/test/MC/AMDGPU/vopc.s Fri Aug 14 13:34:33 2015 @@ -1,5 +1,6 @@ -// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s -// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI +// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI +// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI //===----------------------------------------------------------------------===// // Generic Checks @@ -7,23 +8,28 @@ // src0 sgpr v_cmp_lt_f32 vcc, s2, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, s2, v4 ; encoding: [0x02,0x08,0x82,0x7c] // src0 inline immediate v_cmp_lt_f32 vcc, 0, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, 0, v4 ; encoding: [0x80,0x08,0x82,0x7c] // src0 literal v_cmp_lt_f32 vcc, 10.0, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] +// SICI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x02,0x7c,0x00,0x00,0x20,0x41] +// VI: v_cmp_lt_f32_e32 vcc, 0x41200000, v4 ; encoding: [0xff,0x08,0x82,0x7c,0x00,0x00,0x20,0x41] // src0, src1 max vgpr v_cmp_lt_f32 vcc, v255, v255 -// CHECK: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x03,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, v255, v255 ; encoding: [0xff,0xff,0x83,0x7c] // force 32-bit encoding v_cmp_lt_f32_e32 vcc, v2, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c] //===----------------------------------------------------------------------===// @@ -31,10 +37,12 @@ v_cmp_lt_f32_e32 vcc, v2, v4 //===----------------------------------------------------------------------===// v_cmp_f_f32 vcc, v2, v4 -// CHECK: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] +// SICI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x00,0x7c] +// VI: v_cmp_f_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x80,0x7c] v_cmp_lt_f32 vcc, v2, v4 -// CHECK: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// SICI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x02,0x7c] +// VI: v_cmp_lt_f32_e32 vcc, v2, v4 ; encoding: [0x02,0x09,0x82,0x7c] // TODO: Add tests for the rest of the instructions. _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
