Hi, I am going to be starting work on implementing LLDB support for AArch64/Arm64 scalable vector extension (SVE) in coming weeks. For a quick walk through of SVE please read through this doc here: https://www.kernel.org/doc/Documentation/arm64/sve.txt
In summary it allows hardware + kernel which support SVE to have variable vector register lengths which can be configured as per system requirements on per process or thread basis. I have been informed that there might be some downstream patches and I would like to collaborate with anyone who is willing to contribute their completed or in-progress work. I would also like to open a discussion on how we can implement variable length registers in LLDB and what could be the consequences of those changes. Looking forward to hearing from the community. Thanks! -- Omair Javaid www.linaro.org
_______________________________________________ lldb-dev mailing list lldb-dev@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-dev
