================
@@ -488,6 +508,12 @@ bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg)
const {
return reg == m_sme_regnum_collection[2];
}
+bool RegisterInfoPOSIX_arm64::IsSMERegZT(unsigned reg) const {
+ // ZT0 is part of the SME register set only if SME2 is present.
+ return m_sme_regnum_collection.size() == 4 &&
+ reg == m_sme_regnum_collection.back();
----------------
DavidSpickett wrote:
We can't say "is contained in" because that could be svcr/svg or za.
I've already had to hardcode the assumption that the base sme registers are in
SVCR/SVG/ZA order, and I think we can assume Arm won't add more registers to
SME1. Anything new would be SME2 or a hypothetical SME3.
That means ZT0 will always be the 4th one. So I've updated the check to say if
we have >= 4 registers, and it matches index 3 in the collection. That way this
won't have to change when there are more later. We do have to keep the order
the same overall, but that's unavoidable.
(and tests will fail spectacularly if you get it wrong anyway, though it won't
be fun to debug if you weren't expecting it)
https://github.com/llvm/llvm-project/pull/70205
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