This revision was automatically updated to reflect the committed changes.
Closed by commit rG11de4c724c8e: [lldb][AArch64] Add tests for SME's SVE
register state to… (authored by DavidSpickett).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D157846/new/
https://reviews.llvm.org/D157846
Files:
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
===================================================================
--- lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
+++ lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
@@ -1,5 +1,9 @@
#include <sys/auxv.h>
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
void set_sve_registers() {
// AArch64 SVE extension ISA adds a new set of vector and predicate
registers:
// 32 Z registers, 16 P registers, and 1 FFR register.
@@ -64,8 +68,14 @@
asm volatile("cpy z31.b, p15/z, #32\n\t");
}
-int main() {
- if (getauxval(AT_HWCAP) & HWCAP_SVE) // check if SVE is present
+int main(int argc, char *argv[]) {
+ if (argc > 1) {
+ // Enable streaming mode SVE and the ZA array storage.
+ asm volatile("msr s0_3_c4_c7_3, xzr" /*smstart*/);
+ }
+
+ // If we have SVE or SME, set the SVE registers.
+ if ((getauxval(AT_HWCAP) & HWCAP_SVE) || (getauxval(AT_HWCAP2) & HWCAP2_SME))
set_sve_registers();
return 0; // Set a break point here.
Index:
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
===================================================================
---
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
+++
lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
@@ -120,3 +120,37 @@
)
self.expect("register read data_mask", substrs=["data_mask =
0x"])
self.expect("register read code_mask", substrs=["code_mask =
0x"])
+
+ @no_debug_info_test
+ @skipIf(archs=no_match(["aarch64"]))
+ @skipIf(oslist=no_match(["linux"]))
+ def test_aarch64_dynamic_regset_config_sme(self):
+ """Test AArch64 Dynamic Register sets configuration, but only SME
+ registers."""
+ if not self.isAArch64SME():
+ self.skipTest("SME must be present.")
+
+ self.build()
+ self.line = line_number("main.c", "// Set a break point here.")
+
+ exe = self.getBuildArtifact("a.out")
+ self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+ lldbutil.run_break_set_by_file_and_line(
+ self, "main.c", self.line, num_expected_locations=1
+ )
+ self.runCmd("settings set target.run-args sme")
+ self.runCmd("run", RUN_SUCCEEDED)
+
+ self.expect(
+ "thread backtrace",
+ STOPPED_DUE_TO_BREAKPOINT,
+ substrs=["stop reason = breakpoint 1."],
+ )
+
+ register_sets = self.thread().GetSelectedFrame().GetRegisters()
+
+ ssve_registers = register_sets.GetFirstValueByName(
+ "Scalable Vector Extension Registers")
+ self.assertTrue(ssve_registers.IsValid())
+ self.sve_regs_read_dynamic(ssve_registers)
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
===================================================================
--- lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
+++ lldb/test/API/commands/register/register/aarch64_dynamic_regset/main.c
@@ -1,5 +1,9 @@
#include <sys/auxv.h>
+#ifndef HWCAP2_SME
+#define HWCAP2_SME (1 << 23)
+#endif
+
void set_sve_registers() {
// AArch64 SVE extension ISA adds a new set of vector and predicate registers:
// 32 Z registers, 16 P registers, and 1 FFR register.
@@ -64,8 +68,14 @@
asm volatile("cpy z31.b, p15/z, #32\n\t");
}
-int main() {
- if (getauxval(AT_HWCAP) & HWCAP_SVE) // check if SVE is present
+int main(int argc, char *argv[]) {
+ if (argc > 1) {
+ // Enable streaming mode SVE and the ZA array storage.
+ asm volatile("msr s0_3_c4_c7_3, xzr" /*smstart*/);
+ }
+
+ // If we have SVE or SME, set the SVE registers.
+ if ((getauxval(AT_HWCAP) & HWCAP_SVE) || (getauxval(AT_HWCAP2) & HWCAP2_SME))
set_sve_registers();
return 0; // Set a break point here.
Index: lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
===================================================================
--- lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
+++ lldb/test/API/commands/register/register/aarch64_dynamic_regset/TestArm64DynamicRegsets.py
@@ -120,3 +120,37 @@
)
self.expect("register read data_mask", substrs=["data_mask = 0x"])
self.expect("register read code_mask", substrs=["code_mask = 0x"])
+
+ @no_debug_info_test
+ @skipIf(archs=no_match(["aarch64"]))
+ @skipIf(oslist=no_match(["linux"]))
+ def test_aarch64_dynamic_regset_config_sme(self):
+ """Test AArch64 Dynamic Register sets configuration, but only SME
+ registers."""
+ if not self.isAArch64SME():
+ self.skipTest("SME must be present.")
+
+ self.build()
+ self.line = line_number("main.c", "// Set a break point here.")
+
+ exe = self.getBuildArtifact("a.out")
+ self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+ lldbutil.run_break_set_by_file_and_line(
+ self, "main.c", self.line, num_expected_locations=1
+ )
+ self.runCmd("settings set target.run-args sme")
+ self.runCmd("run", RUN_SUCCEEDED)
+
+ self.expect(
+ "thread backtrace",
+ STOPPED_DUE_TO_BREAKPOINT,
+ substrs=["stop reason = breakpoint 1."],
+ )
+
+ register_sets = self.thread().GetSelectedFrame().GetRegisters()
+
+ ssve_registers = register_sets.GetFirstValueByName(
+ "Scalable Vector Extension Registers")
+ self.assertTrue(ssve_registers.IsValid())
+ self.sve_regs_read_dynamic(ssve_registers)
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