serge-sans-paille updated this revision to Diff 427119.
serge-sans-paille added a comment.
Change the rest case to something that doesn't require me to implement ppc64be
corefile support.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D124760/new/
https://reviews.llvm.org/D124760
Files:
lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
lldb/source/Utility/ArchSpec.cpp
lldb/test/Shell/Breakpoint/Inputs/ppc64le-localentry.s
lldb/test/Shell/Breakpoint/ppc64-localentry.test
lldb/test/Shell/Breakpoint/ppc64le-localentry.test
Index: lldb/test/Shell/Breakpoint/ppc64le-localentry.test
===================================================================
--- /dev/null
+++ lldb/test/Shell/Breakpoint/ppc64le-localentry.test
@@ -0,0 +1,12 @@
+# REQUIRES: powerpc
+#
+# RUN: llvm-mc -triple=powerpc64le -filetype=obj %p/Inputs/ppc64le-localentry.s -o %t
+# RUN: lldb-test breakpoints %t %s | FileCheck %s
+
+breakpoint set -n lfunc
+# CHECK-LABEL: breakpoint set -n lfunc
+# CHECK: Address: {{.*}}`lfunc + 8
+
+breakpoint set -n simple
+# CHECK-LABEL: breakpoint set -n simple
+# CHECK: Address: {{.*}}`simple
Index: lldb/test/Shell/Breakpoint/ppc64-localentry.test
===================================================================
--- lldb/test/Shell/Breakpoint/ppc64-localentry.test
+++ lldb/test/Shell/Breakpoint/ppc64-localentry.test
@@ -1,6 +1,6 @@
# REQUIRES: powerpc
#
-# RUN: llvm-mc -triple=powerpc64le -filetype=obj %p/Inputs/ppc64-localentry.s -o %t
+# RUN: llvm-mc -triple=powerpc64 -filetype=obj %p/Inputs/ppc64-localentry.s -o %t
# RUN: lldb-test breakpoints %t %s | FileCheck %s
breakpoint set -n lfunc
Index: lldb/test/Shell/Breakpoint/Inputs/ppc64le-localentry.s
===================================================================
--- /dev/null
+++ lldb/test/Shell/Breakpoint/Inputs/ppc64le-localentry.s
@@ -0,0 +1,55 @@
+ .text
+ .abiversion 2
+
+ .globl lfunc
+ .p2align 4
+ .type lfunc,@function
+lfunc: # @lfunc
+.Lfunc_begin0:
+.Lfunc_gep0:
+ addis 2, 12, .TOC.-.Lfunc_gep0@ha
+ addi 2, 2, .TOC.-.Lfunc_gep0@l
+.Lfunc_lep0:
+ .localentry lfunc, .Lfunc_lep0-.Lfunc_gep0
+# BB#0:
+ mr 4, 3
+ addis 3, 2, .LC0@toc@ha
+ ld 3, .LC0@toc@l(3)
+ stw 4, -12(1)
+ lwz 4, 0(3)
+ lwz 5, -12(1)
+ mullw 4, 4, 5
+ extsw 3, 4
+ blr
+ .long 0
+ .quad 0
+.Lfunc_end0:
+ .size lfunc, .Lfunc_end0-.Lfunc_begin0
+
+ .globl simple
+ .p2align 4
+ .type simple,@function
+simple: # @simple
+.Lfunc_begin1:
+# %bb.0: # %entry
+ mr 4, 3
+ stw 4, -12(1)
+ lwz 4, -12(1)
+ mulli 4, 4, 10
+ extsw 3, 4
+ blr
+ .long 0
+ .quad 0
+.Lfunc_end1:
+ .size simple, .Lfunc_end1-.Lfunc_begin1
+
+ .section .toc,"aw",@progbits
+.LC0:
+ .tc g_foo[TC],g_foo
+ .type g_foo,@object # @g_foo
+ .data
+ .globl g_foo
+ .p2align 2
+g_foo:
+ .long 2 # 0x2
+ .size g_foo, 4
Index: lldb/source/Utility/ArchSpec.cpp
===================================================================
--- lldb/source/Utility/ArchSpec.cpp
+++ lldb/source/Utility/ArchSpec.cpp
@@ -358,10 +358,10 @@
0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
{ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
- {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
- 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
- {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64, LLDB_INVALID_CPUTYPE,
- 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
+ {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
+ ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
+ {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
+ ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
{ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
{ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
@@ -400,8 +400,8 @@
LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
{ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
- {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE,
- 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR
+ {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
+ 0xFFFFFFFFu}, // AVR
{ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
{ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
Index: lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
===================================================================
--- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
+++ lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
@@ -310,9 +310,19 @@
}
}
+static uint32_t ppc64VariantFromElfFlags(const elf::ELFHeader &header) {
+ uint32_t endian = header.e_ident[EI_DATA];
+ if (endian == ELFDATA2LSB)
+ return ArchSpec::eCore_ppc64le_generic;
+ else
+ return ArchSpec::eCore_ppc64_generic;
+}
+
static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) {
if (header.e_machine == llvm::ELF::EM_MIPS)
return mipsVariantFromElfFlags(header);
+ else if (header.e_machine == llvm::ELF::EM_PPC64)
+ return ppc64VariantFromElfFlags(header);
else if (header.e_machine == llvm::ELF::EM_RISCV)
return riscvVariantFromElfFlags(header);
_______________________________________________
lldb-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
