Author: Michał Górny Date: 2021-10-19T15:51:47+02:00 New Revision: 28e0c34216530087f62da66f3f19ce57211d8eed
URL: https://github.com/llvm/llvm-project/commit/28e0c34216530087f62da66f3f19ce57211d8eed DIFF: https://github.com/llvm/llvm-project/commit/28e0c34216530087f62da66f3f19ce57211d8eed.diff LOG: [lldb] [Process/Utility] Define sN regs on ARM via helper macro This is a piece-wise attempt of reconstructing D112066 with the goal of figuring out which part of the larger change breaks the buildbot. Differential Revision: https://reviews.llvm.org/D112066 Added: Modified: lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h Removed: ################################################################################ diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h index 28af25322afb..1f30cb0723ce 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h @@ -329,6 +329,14 @@ static uint32_t g_q13_contains[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM}; static uint32_t g_q14_contains[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM}; static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM}; +#define FPU_REG(name, size, offset, qreg) \ + { \ + #name, nullptr, size, FPU_OFFSET(offset), eEncodingIEEE754, eFormatFloat, \ + {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ + LLDB_INVALID_REGNUM, fpu_##name }, \ + nullptr, g_##name##_invalidates, \ + } + static RegisterInfo g_register_infos_arm[] = { // NAME ALT SZ OFFSET ENCODING FORMAT // EH_FRAME DWARF GENERIC @@ -542,390 +550,39 @@ static RegisterInfo g_register_infos_arm[] = { nullptr, }, - { - "s0", - nullptr, - 4, - FPU_OFFSET(0), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s0}, - nullptr, - g_s0_invalidates, - }, - { - "s1", - nullptr, - 4, - FPU_OFFSET(1), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s1}, - nullptr, - g_s1_invalidates, - }, - { - "s2", - nullptr, - 4, - FPU_OFFSET(2), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s2}, - nullptr, - g_s2_invalidates, - }, - { - "s3", - nullptr, - 4, - FPU_OFFSET(3), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s3}, - nullptr, - g_s3_invalidates, - }, - { - "s4", - nullptr, - 4, - FPU_OFFSET(4), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s4}, - nullptr, - g_s4_invalidates, - }, - { - "s5", - nullptr, - 4, - FPU_OFFSET(5), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s5}, - nullptr, - g_s5_invalidates, - }, - { - "s6", - nullptr, - 4, - FPU_OFFSET(6), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s6}, - nullptr, - g_s6_invalidates, - }, - { - "s7", - nullptr, - 4, - FPU_OFFSET(7), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s7}, - nullptr, - g_s7_invalidates, - }, - { - "s8", - nullptr, - 4, - FPU_OFFSET(8), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s8}, - nullptr, - g_s8_invalidates, - }, - { - "s9", - nullptr, - 4, - FPU_OFFSET(9), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s9}, - nullptr, - g_s9_invalidates, - }, - { - "s10", - nullptr, - 4, - FPU_OFFSET(10), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s10}, - nullptr, - g_s10_invalidates, - }, - { - "s11", - nullptr, - 4, - FPU_OFFSET(11), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s11}, - nullptr, - g_s11_invalidates, - }, - { - "s12", - nullptr, - 4, - FPU_OFFSET(12), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s12}, - nullptr, - g_s12_invalidates, - }, - { - "s13", - nullptr, - 4, - FPU_OFFSET(13), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s13}, - nullptr, - g_s13_invalidates, - }, - { - "s14", - nullptr, - 4, - FPU_OFFSET(14), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s14}, - nullptr, - g_s14_invalidates, - }, - { - "s15", - nullptr, - 4, - FPU_OFFSET(15), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s15}, - nullptr, - g_s15_invalidates, - }, - { - "s16", - nullptr, - 4, - FPU_OFFSET(16), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s16}, - nullptr, - g_s16_invalidates, - }, - { - "s17", - nullptr, - 4, - FPU_OFFSET(17), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s17}, - nullptr, - g_s17_invalidates, - }, - { - "s18", - nullptr, - 4, - FPU_OFFSET(18), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s18}, - nullptr, - g_s18_invalidates, - }, - { - "s19", - nullptr, - 4, - FPU_OFFSET(19), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s19}, - nullptr, - g_s19_invalidates, - }, - { - "s20", - nullptr, - 4, - FPU_OFFSET(20), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s20}, - nullptr, - g_s20_invalidates, - }, - { - "s21", - nullptr, - 4, - FPU_OFFSET(21), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s21}, - nullptr, - g_s21_invalidates, - }, - { - "s22", - nullptr, - 4, - FPU_OFFSET(22), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s22}, - nullptr, - g_s22_invalidates, - }, - { - "s23", - nullptr, - 4, - FPU_OFFSET(23), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s23}, - nullptr, - g_s23_invalidates, - }, - { - "s24", - nullptr, - 4, - FPU_OFFSET(24), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s24}, - nullptr, - g_s24_invalidates, - }, - { - "s25", - nullptr, - 4, - FPU_OFFSET(25), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s25}, - nullptr, - g_s25_invalidates, - }, - { - "s26", - nullptr, - 4, - FPU_OFFSET(26), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s26}, - nullptr, - g_s26_invalidates, - }, - { - "s27", - nullptr, - 4, - FPU_OFFSET(27), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s27}, - nullptr, - g_s27_invalidates, - }, - { - "s28", - nullptr, - 4, - FPU_OFFSET(28), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s28}, - nullptr, - g_s28_invalidates, - }, - { - "s29", - nullptr, - 4, - FPU_OFFSET(29), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s29}, - nullptr, - g_s29_invalidates, - }, - { - "s30", - nullptr, - 4, - FPU_OFFSET(30), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s30}, - nullptr, - g_s30_invalidates, - }, - { - "s31", - nullptr, - 4, - FPU_OFFSET(31), - eEncodingIEEE754, - eFormatFloat, - {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s31}, - nullptr, - g_s31_invalidates, - }, + FPU_REG(s0, 4, 0, q0), + FPU_REG(s1, 4, 1, q0), + FPU_REG(s2, 4, 2, q0), + FPU_REG(s3, 4, 3, q0), + FPU_REG(s4, 4, 4, q1), + FPU_REG(s5, 4, 5, q1), + FPU_REG(s6, 4, 6, q1), + FPU_REG(s7, 4, 7, q1), + FPU_REG(s8, 4, 8, q2), + FPU_REG(s9, 4, 9, q2), + FPU_REG(s10, 4, 10, q2), + FPU_REG(s11, 4, 11, q2), + FPU_REG(s12, 4, 12, q3), + FPU_REG(s13, 4, 13, q3), + FPU_REG(s14, 4, 14, q3), + FPU_REG(s15, 4, 15, q3), + FPU_REG(s16, 4, 16, q4), + FPU_REG(s17, 4, 17, q4), + FPU_REG(s18, 4, 18, q4), + FPU_REG(s19, 4, 19, q4), + FPU_REG(s20, 4, 20, q5), + FPU_REG(s21, 4, 21, q5), + FPU_REG(s22, 4, 22, q5), + FPU_REG(s23, 4, 23, q5), + FPU_REG(s24, 4, 24, q6), + FPU_REG(s25, 4, 25, q6), + FPU_REG(s26, 4, 26, q6), + FPU_REG(s27, 4, 27, q6), + FPU_REG(s28, 4, 28, q7), + FPU_REG(s29, 4, 29, q7), + FPU_REG(s30, 4, 30, q7), + FPU_REG(s31, 4, 31, q7), + { "fpscr", nullptr, _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
