Author: Michał Górny Date: 2021-10-19T15:33:39+02:00 New Revision: 7df912c65d1963c5403f1d645329b20f7e2d60ea
URL: https://github.com/llvm/llvm-project/commit/7df912c65d1963c5403f1d645329b20f7e2d60ea DIFF: https://github.com/llvm/llvm-project/commit/7df912c65d1963c5403f1d645329b20f7e2d60ea.diff LOG: Revert "[lldb] [Process/Utility] Fix value_regs/invalidate_regs for ARM" This reverts commit 1c2c67b46b55a2a81ebc988c829e2eee13a4fec6. Something's still wrong. Added: Modified: lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h Removed: ################################################################################ diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h index ace2e5a9f68b0..9eba19c071e3b 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h @@ -254,38 +254,39 @@ static uint32_t g_s29_invalidates[] = {fpu_d14, fpu_q7, LLDB_INVALID_REGNUM}; static uint32_t g_s30_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; static uint32_t g_s31_invalidates[] = {fpu_d15, fpu_q7, LLDB_INVALID_REGNUM}; -static uint32_t g_d0_invalidates[] = {fpu_q0, fpu_s0, fpu_s1, - LLDB_INVALID_REGNUM}; -static uint32_t g_d1_invalidates[] = {fpu_q0, fpu_s2, fpu_s3, - LLDB_INVALID_REGNUM}; -static uint32_t g_d2_invalidates[] = {fpu_q1, fpu_s4, fpu_s5, - LLDB_INVALID_REGNUM}; -static uint32_t g_d3_invalidates[] = {fpu_q1, fpu_s6, fpu_s7, - LLDB_INVALID_REGNUM}; -static uint32_t g_d4_invalidates[] = {fpu_q2, fpu_s8, fpu_s9, - LLDB_INVALID_REGNUM}; -static uint32_t g_d5_invalidates[] = {fpu_q2, fpu_s10, fpu_s11, - LLDB_INVALID_REGNUM}; -static uint32_t g_d6_invalidates[] = {fpu_q3, fpu_s12, fpu_s13, - LLDB_INVALID_REGNUM}; -static uint32_t g_d7_invalidates[] = {fpu_q3, fpu_s14, fpu_s15, - LLDB_INVALID_REGNUM}; -static uint32_t g_d8_invalidates[] = {fpu_q4, fpu_s16, fpu_s17, - LLDB_INVALID_REGNUM}; -static uint32_t g_d9_invalidates[] = {fpu_q4, fpu_s18, fpu_s19, - LLDB_INVALID_REGNUM}; -static uint32_t g_d10_invalidates[] = {fpu_q5, fpu_s20, fpu_s21, - LLDB_INVALID_REGNUM}; -static uint32_t g_d11_invalidates[] = {fpu_q5, fpu_s22, fpu_s23, - LLDB_INVALID_REGNUM}; -static uint32_t g_d12_invalidates[] = {fpu_q6, fpu_s24, fpu_s25, - LLDB_INVALID_REGNUM}; -static uint32_t g_d13_invalidates[] = {fpu_q6, fpu_s26, fpu_s27, - LLDB_INVALID_REGNUM}; -static uint32_t g_d14_invalidates[] = {fpu_q7, fpu_s28, fpu_s29, - LLDB_INVALID_REGNUM}; -static uint32_t g_d15_invalidates[] = {fpu_q7, fpu_s30, fpu_s31, - LLDB_INVALID_REGNUM}; +static uint32_t g_d0_contains[] = {fpu_s0, fpu_s1, LLDB_INVALID_REGNUM}; +static uint32_t g_d1_contains[] = {fpu_s2, fpu_s3, LLDB_INVALID_REGNUM}; +static uint32_t g_d2_contains[] = {fpu_s4, fpu_s5, LLDB_INVALID_REGNUM}; +static uint32_t g_d3_contains[] = {fpu_s6, fpu_s7, LLDB_INVALID_REGNUM}; +static uint32_t g_d4_contains[] = {fpu_s8, fpu_s9, LLDB_INVALID_REGNUM}; +static uint32_t g_d5_contains[] = {fpu_s10, fpu_s11, LLDB_INVALID_REGNUM}; +static uint32_t g_d6_contains[] = {fpu_s12, fpu_s13, LLDB_INVALID_REGNUM}; +static uint32_t g_d7_contains[] = {fpu_s14, fpu_s15, LLDB_INVALID_REGNUM}; +static uint32_t g_d8_contains[] = {fpu_s16, fpu_s17, LLDB_INVALID_REGNUM}; +static uint32_t g_d9_contains[] = {fpu_s18, fpu_s19, LLDB_INVALID_REGNUM}; +static uint32_t g_d10_contains[] = {fpu_s20, fpu_s21, LLDB_INVALID_REGNUM}; +static uint32_t g_d11_contains[] = {fpu_s22, fpu_s23, LLDB_INVALID_REGNUM}; +static uint32_t g_d12_contains[] = {fpu_s24, fpu_s25, LLDB_INVALID_REGNUM}; +static uint32_t g_d13_contains[] = {fpu_s26, fpu_s27, LLDB_INVALID_REGNUM}; +static uint32_t g_d14_contains[] = {fpu_s28, fpu_s29, LLDB_INVALID_REGNUM}; +static uint32_t g_d15_contains[] = {fpu_s30, fpu_s31, LLDB_INVALID_REGNUM}; + +static uint32_t g_d0_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM}; +static uint32_t g_d1_invalidates[] = {fpu_q0, LLDB_INVALID_REGNUM}; +static uint32_t g_d2_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM}; +static uint32_t g_d3_invalidates[] = {fpu_q1, LLDB_INVALID_REGNUM}; +static uint32_t g_d4_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM}; +static uint32_t g_d5_invalidates[] = {fpu_q2, LLDB_INVALID_REGNUM}; +static uint32_t g_d6_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM}; +static uint32_t g_d7_invalidates[] = {fpu_q3, LLDB_INVALID_REGNUM}; +static uint32_t g_d8_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM}; +static uint32_t g_d9_invalidates[] = {fpu_q4, LLDB_INVALID_REGNUM}; +static uint32_t g_d10_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM}; +static uint32_t g_d11_invalidates[] = {fpu_q5, LLDB_INVALID_REGNUM}; +static uint32_t g_d12_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM}; +static uint32_t g_d13_invalidates[] = {fpu_q6, LLDB_INVALID_REGNUM}; +static uint32_t g_d14_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM}; +static uint32_t g_d15_invalidates[] = {fpu_q7, LLDB_INVALID_REGNUM}; static uint32_t g_d16_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; static uint32_t g_d17_invalidates[] = {fpu_q8, LLDB_INVALID_REGNUM}; static uint32_t g_d18_invalidates[] = {fpu_q9, LLDB_INVALID_REGNUM}; @@ -303,64 +304,30 @@ static uint32_t g_d29_invalidates[] = {fpu_q14, LLDB_INVALID_REGNUM}; static uint32_t g_d30_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; static uint32_t g_d31_invalidates[] = {fpu_q15, LLDB_INVALID_REGNUM}; -static uint32_t g_q0_invalidates[] = { +static uint32_t g_q0_contains[] = { fpu_d0, fpu_d1, fpu_s0, fpu_s1, fpu_s2, fpu_s3, LLDB_INVALID_REGNUM}; -static uint32_t g_q1_invalidates[] = { +static uint32_t g_q1_contains[] = { fpu_d2, fpu_d3, fpu_s4, fpu_s5, fpu_s6, fpu_s7, LLDB_INVALID_REGNUM}; -static uint32_t g_q2_invalidates[] = { +static uint32_t g_q2_contains[] = { fpu_d4, fpu_d5, fpu_s8, fpu_s9, fpu_s10, fpu_s11, LLDB_INVALID_REGNUM}; -static uint32_t g_q3_invalidates[] = { +static uint32_t g_q3_contains[] = { fpu_d6, fpu_d7, fpu_s12, fpu_s13, fpu_s14, fpu_s15, LLDB_INVALID_REGNUM}; -static uint32_t g_q4_invalidates[] = { +static uint32_t g_q4_contains[] = { fpu_d8, fpu_d9, fpu_s16, fpu_s17, fpu_s18, fpu_s19, LLDB_INVALID_REGNUM}; -static uint32_t g_q5_invalidates[] = { +static uint32_t g_q5_contains[] = { fpu_d10, fpu_d11, fpu_s20, fpu_s21, fpu_s22, fpu_s23, LLDB_INVALID_REGNUM}; -static uint32_t g_q6_invalidates[] = { +static uint32_t g_q6_contains[] = { fpu_d12, fpu_d13, fpu_s24, fpu_s25, fpu_s26, fpu_s27, LLDB_INVALID_REGNUM}; -static uint32_t g_q7_invalidates[] = { +static uint32_t g_q7_contains[] = { fpu_d14, fpu_d15, fpu_s28, fpu_s29, fpu_s30, fpu_s31, LLDB_INVALID_REGNUM}; -static uint32_t g_q8_invalidates[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM}; -static uint32_t g_q9_invalidates[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM}; -static uint32_t g_q10_invalidates[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM}; -static uint32_t g_q11_invalidates[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM}; -static uint32_t g_q12_invalidates[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM}; -static uint32_t g_q13_invalidates[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM}; -static uint32_t g_q14_invalidates[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM}; -static uint32_t g_q15_invalidates[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM}; - -static uint32_t g_q0_contained[] = {fpu_q0, LLDB_INVALID_REGNUM}; -static uint32_t g_q1_contained[] = {fpu_q1, LLDB_INVALID_REGNUM}; -static uint32_t g_q2_contained[] = {fpu_q2, LLDB_INVALID_REGNUM}; -static uint32_t g_q3_contained[] = {fpu_q3, LLDB_INVALID_REGNUM}; -static uint32_t g_q4_contained[] = {fpu_q4, LLDB_INVALID_REGNUM}; -static uint32_t g_q5_contained[] = {fpu_q5, LLDB_INVALID_REGNUM}; -static uint32_t g_q6_contained[] = {fpu_q6, LLDB_INVALID_REGNUM}; -static uint32_t g_q7_contained[] = {fpu_q7, LLDB_INVALID_REGNUM}; -static uint32_t g_q8_contained[] = {fpu_q8, LLDB_INVALID_REGNUM}; -static uint32_t g_q9_contained[] = {fpu_q9, LLDB_INVALID_REGNUM}; -static uint32_t g_q10_contained[] = {fpu_q10, LLDB_INVALID_REGNUM}; -static uint32_t g_q11_contained[] = {fpu_q11, LLDB_INVALID_REGNUM}; -static uint32_t g_q12_contained[] = {fpu_q12, LLDB_INVALID_REGNUM}; -static uint32_t g_q13_contained[] = {fpu_q13, LLDB_INVALID_REGNUM}; -static uint32_t g_q14_contained[] = {fpu_q14, LLDB_INVALID_REGNUM}; -static uint32_t g_q15_contained[] = {fpu_q15, LLDB_INVALID_REGNUM}; - -#define FPU_REG(name, size, offset, qreg) \ - { \ - #name, nullptr, size, FPU_OFFSET(offset), eEncodingIEEE754, eFormatFloat, \ - {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ - LLDB_INVALID_REGNUM, fpu_##name }, \ - g_##qreg##_contained, g_##name##_invalidates, \ - } - -#define FPU_QREG(name, offset) \ - { \ - #name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \ - eFormatVectorOfUInt8, \ - {LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \ - LLDB_INVALID_REGNUM, fpu_##name }, \ - nullptr, g_##name##_invalidates, \ - } +static uint32_t g_q8_contains[] = {fpu_d16, fpu_d17, LLDB_INVALID_REGNUM}; +static uint32_t g_q9_contains[] = {fpu_d18, fpu_d19, LLDB_INVALID_REGNUM}; +static uint32_t g_q10_contains[] = {fpu_d20, fpu_d21, LLDB_INVALID_REGNUM}; +static uint32_t g_q11_contains[] = {fpu_d22, fpu_d23, LLDB_INVALID_REGNUM}; +static uint32_t g_q12_contains[] = {fpu_d24, fpu_d25, LLDB_INVALID_REGNUM}; +static uint32_t g_q13_contains[] = {fpu_d26, fpu_d27, LLDB_INVALID_REGNUM}; +static uint32_t g_q14_contains[] = {fpu_d28, fpu_d29, LLDB_INVALID_REGNUM}; +static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM}; static RegisterInfo g_register_infos_arm[] = { // NAME ALT SZ OFFSET ENCODING FORMAT @@ -370,342 +337,1114 @@ static RegisterInfo g_register_infos_arm[] = { // ==================== =================== =================== // ========================== =================== ============= // ============== ================= - { - "r0", - nullptr, - 4, - GPR_OFFSET(0), - eEncodingUint, - eFormatHex, - {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, - gpr_r0}, - nullptr, - nullptr, - }, - { - "r1", - nullptr, - 4, - GPR_OFFSET(1), - eEncodingUint, - eFormatHex, - {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, - gpr_r1}, - nullptr, - nullptr, - }, - { - "r2", - nullptr, - 4, - GPR_OFFSET(2), - eEncodingUint, - eFormatHex, - {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, - gpr_r2}, - nullptr, - nullptr, - }, - { - "r3", - nullptr, - 4, - GPR_OFFSET(3), - eEncodingUint, - eFormatHex, - {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, - gpr_r3}, - nullptr, - nullptr, - }, - { - "r4", - nullptr, - 4, - GPR_OFFSET(4), - eEncodingUint, - eFormatHex, - {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r4}, - nullptr, - nullptr, - }, - { - "r5", - nullptr, - 4, - GPR_OFFSET(5), - eEncodingUint, - eFormatHex, - {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r5}, - nullptr, - nullptr, - }, - { - "r6", - nullptr, - 4, - GPR_OFFSET(6), - eEncodingUint, - eFormatHex, - {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r6}, - nullptr, - nullptr, - }, - { - "r7", - nullptr, - 4, - GPR_OFFSET(7), - eEncodingUint, - eFormatHex, - {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r7}, - nullptr, - nullptr, - }, - { - "r8", - nullptr, - 4, - GPR_OFFSET(8), - eEncodingUint, - eFormatHex, - {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r8}, - nullptr, - nullptr, - }, - { - "r9", - nullptr, - 4, - GPR_OFFSET(9), - eEncodingUint, - eFormatHex, - {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r9}, - nullptr, - nullptr, - }, - { - "r10", - nullptr, - 4, - GPR_OFFSET(10), - eEncodingUint, - eFormatHex, - {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r10}, - nullptr, - nullptr, - }, - { - "r11", - nullptr, - 4, - GPR_OFFSET(11), - eEncodingUint, - eFormatHex, - {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, - gpr_r11}, - nullptr, - nullptr, - }, - { - "r12", - nullptr, - 4, - GPR_OFFSET(12), - eEncodingUint, - eFormatHex, - {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - gpr_r12}, - nullptr, - nullptr, - }, - { - "sp", - "r13", - 4, - GPR_OFFSET(13), - eEncodingUint, - eFormatHex, - {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, - gpr_sp}, - nullptr, - nullptr, - }, - { - "lr", - "r14", - 4, - GPR_OFFSET(14), - eEncodingUint, - eFormatHex, - {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, - gpr_lr}, - nullptr, - nullptr, - }, - { - "pc", - "r15", - 4, - GPR_OFFSET(15), - eEncodingUint, - eFormatHex, - {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, - gpr_pc}, - nullptr, - nullptr, - }, - { - "cpsr", - "psr", - 4, - GPR_OFFSET(16), - eEncodingUint, - eFormatHex, - {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, - LLDB_INVALID_REGNUM, gpr_cpsr}, - nullptr, - nullptr, - }, - - FPU_REG(s0, 4, 0, q0), - FPU_REG(s1, 4, 1, q0), - FPU_REG(s2, 4, 2, q0), - FPU_REG(s3, 4, 3, q0), - FPU_REG(s4, 4, 4, q1), - FPU_REG(s5, 4, 5, q1), - FPU_REG(s6, 4, 6, q1), - FPU_REG(s7, 4, 7, q1), - FPU_REG(s8, 4, 8, q2), - FPU_REG(s9, 4, 9, q2), - FPU_REG(s10, 4, 10, q2), - FPU_REG(s11, 4, 11, q2), - FPU_REG(s12, 4, 12, q3), - FPU_REG(s13, 4, 13, q3), - FPU_REG(s14, 4, 14, q3), - FPU_REG(s15, 4, 15, q3), - FPU_REG(s16, 4, 16, q4), - FPU_REG(s17, 4, 17, q4), - FPU_REG(s18, 4, 18, q4), - FPU_REG(s19, 4, 19, q4), - FPU_REG(s20, 4, 20, q5), - FPU_REG(s21, 4, 21, q5), - FPU_REG(s22, 4, 22, q5), - FPU_REG(s23, 4, 23, q5), - FPU_REG(s24, 4, 24, q6), - FPU_REG(s25, 4, 25, q6), - FPU_REG(s26, 4, 26, q6), - FPU_REG(s27, 4, 27, q6), - FPU_REG(s28, 4, 28, q7), - FPU_REG(s29, 4, 29, q7), - FPU_REG(s30, 4, 30, q7), - FPU_REG(s31, 4, 31, q7), - - { - "fpscr", - nullptr, - 4, - FPSCR_OFFSET, - eEncodingUint, - eFormatHex, - {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_fpscr}, - nullptr, - nullptr, - }, - - FPU_REG(d0, 8, 0, q0), - FPU_REG(d1, 8, 2, q0), - FPU_REG(d2, 8, 4, q1), - FPU_REG(d3, 8, 6, q1), - FPU_REG(d4, 8, 8, q2), - FPU_REG(d5, 8, 10, q2), - FPU_REG(d6, 8, 12, q3), - FPU_REG(d7, 8, 14, q3), - FPU_REG(d8, 8, 16, q4), - FPU_REG(d9, 8, 18, q4), - FPU_REG(d10, 8, 20, q5), - FPU_REG(d11, 8, 22, q5), - FPU_REG(d12, 8, 24, q6), - FPU_REG(d13, 8, 26, q6), - FPU_REG(d14, 8, 28, q7), - FPU_REG(d15, 8, 30, q7), - FPU_REG(d16, 8, 32, q8), - FPU_REG(d17, 8, 34, q8), - FPU_REG(d18, 8, 36, q9), - FPU_REG(d19, 8, 38, q9), - FPU_REG(d20, 8, 40, q10), - FPU_REG(d21, 8, 42, q10), - FPU_REG(d22, 8, 44, q11), - FPU_REG(d23, 8, 46, q11), - FPU_REG(d24, 8, 48, q12), - FPU_REG(d25, 8, 50, q12), - FPU_REG(d26, 8, 52, q13), - FPU_REG(d27, 8, 54, q13), - FPU_REG(d28, 8, 56, q14), - FPU_REG(d29, 8, 58, q14), - FPU_REG(d30, 8, 60, q15), - FPU_REG(d31, 8, 62, q15), - - FPU_QREG(q0, 0), - FPU_QREG(q1, 4), - FPU_QREG(q2, 8), - FPU_QREG(q3, 12), - FPU_QREG(q4, 16), - FPU_QREG(q5, 20), - FPU_QREG(q6, 24), - FPU_QREG(q7, 28), - FPU_QREG(q8, 32), - FPU_QREG(q9, 36), - FPU_QREG(q10, 40), - FPU_QREG(q11, 44), - FPU_QREG(q12, 48), - FPU_QREG(q13, 52), - FPU_QREG(q14, 56), - FPU_QREG(q15, 60), - - { - "exception", - nullptr, - 4, - EXC_OFFSET(0), - eEncodingUint, - eFormatHex, - {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, exc_exception}, - nullptr, - nullptr, - }, - { - "fsr", - nullptr, - 4, - EXC_OFFSET(1), - eEncodingUint, - eFormatHex, - {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, exc_fsr}, - nullptr, - nullptr, - }, - { - "far", - nullptr, - 4, - EXC_OFFSET(2), - eEncodingUint, - eFormatHex, - {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, exc_far}, - nullptr, - nullptr, + {"r0", + nullptr, + 4, + GPR_OFFSET(0), + eEncodingUint, + eFormatHex, + {ehframe_r0, dwarf_r0, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM, + gpr_r0}, + nullptr, + nullptr, + }, + {"r1", + nullptr, + 4, + GPR_OFFSET(1), + eEncodingUint, + eFormatHex, + {ehframe_r1, dwarf_r1, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM, + gpr_r1}, + nullptr, + nullptr, + }, + {"r2", + nullptr, + 4, + GPR_OFFSET(2), + eEncodingUint, + eFormatHex, + {ehframe_r2, dwarf_r2, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM, + gpr_r2}, + nullptr, + nullptr, + }, + {"r3", + nullptr, + 4, + GPR_OFFSET(3), + eEncodingUint, + eFormatHex, + {ehframe_r3, dwarf_r3, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM, + gpr_r3}, + nullptr, + nullptr, + }, + {"r4", + nullptr, + 4, + GPR_OFFSET(4), + eEncodingUint, + eFormatHex, + {ehframe_r4, dwarf_r4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r4}, + nullptr, + nullptr, + }, + {"r5", + nullptr, + 4, + GPR_OFFSET(5), + eEncodingUint, + eFormatHex, + {ehframe_r5, dwarf_r5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r5}, + nullptr, + nullptr, + }, + {"r6", + nullptr, + 4, + GPR_OFFSET(6), + eEncodingUint, + eFormatHex, + {ehframe_r6, dwarf_r6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r6}, + nullptr, + nullptr, + }, + {"r7", + nullptr, + 4, + GPR_OFFSET(7), + eEncodingUint, + eFormatHex, + {ehframe_r7, dwarf_r7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r7}, + nullptr, + nullptr, + }, + {"r8", + nullptr, + 4, + GPR_OFFSET(8), + eEncodingUint, + eFormatHex, + {ehframe_r8, dwarf_r8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r8}, + nullptr, + nullptr, + }, + {"r9", + nullptr, + 4, + GPR_OFFSET(9), + eEncodingUint, + eFormatHex, + {ehframe_r9, dwarf_r9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, gpr_r9}, + nullptr, + nullptr, + }, + {"r10", + nullptr, + 4, + GPR_OFFSET(10), + eEncodingUint, + eFormatHex, + {ehframe_r10, dwarf_r10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + gpr_r10}, + nullptr, + nullptr, + }, + {"r11", + nullptr, + 4, + GPR_OFFSET(11), + eEncodingUint, + eFormatHex, + {ehframe_r11, dwarf_r11, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM, + gpr_r11}, + nullptr, + nullptr, + }, + {"r12", + nullptr, + 4, + GPR_OFFSET(12), + eEncodingUint, + eFormatHex, + {ehframe_r12, dwarf_r12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + gpr_r12}, + nullptr, + nullptr, + }, + {"sp", + "r13", + 4, + GPR_OFFSET(13), + eEncodingUint, + eFormatHex, + {ehframe_sp, dwarf_sp, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM, + gpr_sp}, + nullptr, + nullptr, + }, + {"lr", + "r14", + 4, + GPR_OFFSET(14), + eEncodingUint, + eFormatHex, + {ehframe_lr, dwarf_lr, LLDB_REGNUM_GENERIC_RA, LLDB_INVALID_REGNUM, + gpr_lr}, + nullptr, + nullptr, + }, + {"pc", + "r15", + 4, + GPR_OFFSET(15), + eEncodingUint, + eFormatHex, + {ehframe_pc, dwarf_pc, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM, + gpr_pc}, + nullptr, + nullptr, + }, + {"cpsr", + "psr", + 4, + GPR_OFFSET(16), + eEncodingUint, + eFormatHex, + {ehframe_cpsr, dwarf_cpsr, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM, + gpr_cpsr}, + nullptr, + nullptr, + }, + + {"s0", + nullptr, + 4, + FPU_OFFSET(0), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s0}, + nullptr, + g_s0_invalidates, + }, + {"s1", + nullptr, + 4, + FPU_OFFSET(1), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s1}, + nullptr, + g_s1_invalidates, + }, + {"s2", + nullptr, + 4, + FPU_OFFSET(2), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s2}, + nullptr, + g_s2_invalidates, + }, + {"s3", + nullptr, + 4, + FPU_OFFSET(3), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s3}, + nullptr, + g_s3_invalidates, + }, + {"s4", + nullptr, + 4, + FPU_OFFSET(4), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s4}, + nullptr, + g_s4_invalidates, + }, + {"s5", + nullptr, + 4, + FPU_OFFSET(5), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s5}, + nullptr, + g_s5_invalidates, + }, + {"s6", + nullptr, + 4, + FPU_OFFSET(6), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s6}, + nullptr, + g_s6_invalidates, + }, + {"s7", + nullptr, + 4, + FPU_OFFSET(7), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s7}, + nullptr, + g_s7_invalidates, + }, + {"s8", + nullptr, + 4, + FPU_OFFSET(8), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s8}, + nullptr, + g_s8_invalidates, + }, + {"s9", + nullptr, + 4, + FPU_OFFSET(9), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s9}, + nullptr, + g_s9_invalidates, + }, + {"s10", + nullptr, + 4, + FPU_OFFSET(10), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s10}, + nullptr, + g_s10_invalidates, + }, + {"s11", + nullptr, + 4, + FPU_OFFSET(11), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s11}, + nullptr, + g_s11_invalidates, + }, + {"s12", + nullptr, + 4, + FPU_OFFSET(12), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s12}, + nullptr, + g_s12_invalidates, + }, + {"s13", + nullptr, + 4, + FPU_OFFSET(13), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s13}, + nullptr, + g_s13_invalidates, + }, + {"s14", + nullptr, + 4, + FPU_OFFSET(14), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s14}, + nullptr, + g_s14_invalidates, + }, + {"s15", + nullptr, + 4, + FPU_OFFSET(15), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s15}, + nullptr, + g_s15_invalidates, + }, + {"s16", + nullptr, + 4, + FPU_OFFSET(16), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s16}, + nullptr, + g_s16_invalidates, + }, + {"s17", + nullptr, + 4, + FPU_OFFSET(17), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s17}, + nullptr, + g_s17_invalidates, + }, + {"s18", + nullptr, + 4, + FPU_OFFSET(18), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s18}, + nullptr, + g_s18_invalidates, + }, + {"s19", + nullptr, + 4, + FPU_OFFSET(19), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s19}, + nullptr, + g_s19_invalidates, + }, + {"s20", + nullptr, + 4, + FPU_OFFSET(20), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s20}, + nullptr, + g_s20_invalidates, + }, + {"s21", + nullptr, + 4, + FPU_OFFSET(21), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s21}, + nullptr, + g_s21_invalidates, + }, + {"s22", + nullptr, + 4, + FPU_OFFSET(22), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s22}, + nullptr, + g_s22_invalidates, + }, + {"s23", + nullptr, + 4, + FPU_OFFSET(23), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s23}, + nullptr, + g_s23_invalidates, + }, + {"s24", + nullptr, + 4, + FPU_OFFSET(24), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s24}, + nullptr, + g_s24_invalidates, + }, + {"s25", + nullptr, + 4, + FPU_OFFSET(25), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s25}, + nullptr, + g_s25_invalidates, + }, + {"s26", + nullptr, + 4, + FPU_OFFSET(26), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s26}, + nullptr, + g_s26_invalidates, + }, + {"s27", + nullptr, + 4, + FPU_OFFSET(27), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s27}, + nullptr, + g_s27_invalidates, + }, + {"s28", + nullptr, + 4, + FPU_OFFSET(28), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s28}, + nullptr, + g_s28_invalidates, + }, + {"s29", + nullptr, + 4, + FPU_OFFSET(29), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s29}, + nullptr, + g_s29_invalidates, + }, + {"s30", + nullptr, + 4, + FPU_OFFSET(30), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s30}, + nullptr, + g_s30_invalidates, + }, + {"s31", + nullptr, + 4, + FPU_OFFSET(31), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_s31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_s31}, + nullptr, + g_s31_invalidates, + }, + {"fpscr", + nullptr, + 4, + FPSCR_OFFSET, + eEncodingUint, + eFormatHex, + {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, fpu_fpscr}, + nullptr, + nullptr, + }, + + {"d0", + nullptr, + 8, + FPU_OFFSET(0), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d0}, + g_d0_contains, + g_d0_invalidates, + }, + {"d1", + nullptr, + 8, + FPU_OFFSET(2), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d1}, + g_d1_contains, + g_d1_invalidates, + }, + {"d2", + nullptr, + 8, + FPU_OFFSET(4), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d2}, + g_d2_contains, + g_d2_invalidates, + }, + {"d3", + nullptr, + 8, + FPU_OFFSET(6), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d3}, + g_d3_contains, + g_d3_invalidates, + }, + {"d4", + nullptr, + 8, + FPU_OFFSET(8), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d4}, + g_d4_contains, + g_d4_invalidates, + }, + {"d5", + nullptr, + 8, + FPU_OFFSET(10), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d5}, + g_d5_contains, + g_d5_invalidates, + }, + {"d6", + nullptr, + 8, + FPU_OFFSET(12), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d6}, + g_d6_contains, + g_d6_invalidates, + }, + {"d7", + nullptr, + 8, + FPU_OFFSET(14), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d7}, + g_d7_contains, + g_d7_invalidates, + }, + {"d8", + nullptr, + 8, + FPU_OFFSET(16), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d8}, + g_d8_contains, + g_d8_invalidates, + }, + {"d9", + nullptr, + 8, + FPU_OFFSET(18), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d9}, + g_d9_contains, + g_d9_invalidates, + }, + {"d10", + nullptr, + 8, + FPU_OFFSET(20), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d10}, + g_d10_contains, + g_d10_invalidates, + }, + {"d11", + nullptr, + 8, + FPU_OFFSET(22), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d11}, + g_d11_contains, + g_d11_invalidates, + }, + {"d12", + nullptr, + 8, + FPU_OFFSET(24), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d12}, + g_d12_contains, + g_d12_invalidates, + }, + {"d13", + nullptr, + 8, + FPU_OFFSET(26), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d13}, + g_d13_contains, + g_d13_invalidates, + }, + {"d14", + nullptr, + 8, + FPU_OFFSET(28), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d14}, + g_d14_contains, + g_d14_invalidates, + }, + {"d15", + nullptr, + 8, + FPU_OFFSET(30), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d15}, + g_d15_contains, + g_d15_invalidates, + }, + {"d16", + nullptr, + 8, + FPU_OFFSET(32), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d16, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d16}, + nullptr, + g_d16_invalidates, + }, + {"d17", + nullptr, + 8, + FPU_OFFSET(34), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d17, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d17}, + nullptr, + g_d17_invalidates, + }, + {"d18", + nullptr, + 8, + FPU_OFFSET(36), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d18, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d18}, + nullptr, + g_d18_invalidates, + }, + {"d19", + nullptr, + 8, + FPU_OFFSET(38), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d19, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d19}, + nullptr, + g_d19_invalidates, + }, + {"d20", + nullptr, + 8, + FPU_OFFSET(40), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d20, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d20}, + nullptr, + g_d20_invalidates, + }, + {"d21", + nullptr, + 8, + FPU_OFFSET(42), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d21, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d21}, + nullptr, + g_d21_invalidates, + }, + {"d22", + nullptr, + 8, + FPU_OFFSET(44), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d22, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d22}, + nullptr, + g_d22_invalidates, + }, + {"d23", + nullptr, + 8, + FPU_OFFSET(46), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d23, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d23}, + nullptr, + g_d23_invalidates, + }, + {"d24", + nullptr, + 8, + FPU_OFFSET(48), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d24, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d24}, + nullptr, + g_d24_invalidates, + }, + {"d25", + nullptr, + 8, + FPU_OFFSET(50), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d25, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d25}, + nullptr, + g_d25_invalidates, + }, + {"d26", + nullptr, + 8, + FPU_OFFSET(52), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d26, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d26}, + nullptr, + g_d26_invalidates, + }, + {"d27", + nullptr, + 8, + FPU_OFFSET(54), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d27, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d27}, + nullptr, + g_d27_invalidates, + }, + {"d28", + nullptr, + 8, + FPU_OFFSET(56), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d28, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d28}, + nullptr, + g_d28_invalidates, + }, + {"d29", + nullptr, + 8, + FPU_OFFSET(58), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d29, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d29}, + nullptr, + g_d29_invalidates, + }, + {"d30", + nullptr, + 8, + FPU_OFFSET(60), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d30, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d30}, + nullptr, + g_d30_invalidates, + }, + {"d31", + nullptr, + 8, + FPU_OFFSET(62), + eEncodingIEEE754, + eFormatFloat, + {LLDB_INVALID_REGNUM, dwarf_d31, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_d31}, + nullptr, + g_d31_invalidates, + }, + + {"q0", + nullptr, + 16, + FPU_OFFSET(0), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q0}, + g_q0_contains, + nullptr, + }, + {"q1", + nullptr, + 16, + FPU_OFFSET(4), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q1}, + g_q1_contains, + nullptr, + }, + {"q2", + nullptr, + 16, + FPU_OFFSET(8), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q2}, + g_q2_contains, + nullptr, + }, + {"q3", + nullptr, + 16, + FPU_OFFSET(12), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q3}, + g_q3_contains, + nullptr, + }, + {"q4", + nullptr, + 16, + FPU_OFFSET(16), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q4, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q4}, + g_q4_contains, + nullptr, + }, + {"q5", + nullptr, + 16, + FPU_OFFSET(20), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q5, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q5}, + g_q5_contains, + nullptr, + }, + {"q6", + nullptr, + 16, + FPU_OFFSET(24), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q6, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q6}, + g_q6_contains, + nullptr, + }, + {"q7", + nullptr, + 16, + FPU_OFFSET(28), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q7}, + g_q7_contains, + nullptr, + }, + {"q8", + nullptr, + 16, + FPU_OFFSET(32), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q8, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q8}, + g_q8_contains, + nullptr, + }, + {"q9", + nullptr, + 16, + FPU_OFFSET(36), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q9, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q9}, + g_q9_contains, + nullptr, + }, + {"q10", + nullptr, + 16, + FPU_OFFSET(40), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q10, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q10}, + g_q10_contains, + nullptr, + }, + {"q11", + nullptr, + 16, + FPU_OFFSET(44), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q11, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q11}, + g_q11_contains, + nullptr, + }, + {"q12", + nullptr, + 16, + FPU_OFFSET(48), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q12, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q12}, + g_q12_contains, + nullptr, + }, + {"q13", + nullptr, + 16, + FPU_OFFSET(52), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q13, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q13}, + g_q13_contains, + nullptr, + }, + {"q14", + nullptr, + 16, + FPU_OFFSET(56), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q14, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q14}, + g_q14_contains, + nullptr, + }, + {"q15", + nullptr, + 16, + FPU_OFFSET(60), + eEncodingVector, + eFormatVectorOfUInt8, + {LLDB_INVALID_REGNUM, dwarf_q15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + fpu_q15}, + g_q15_contains, + nullptr, + }, + + {"exception", + nullptr, + 4, + EXC_OFFSET(0), + eEncodingUint, + eFormatHex, + {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, exc_exception}, + nullptr, + nullptr, + }, + {"fsr", + nullptr, + 4, + EXC_OFFSET(1), + eEncodingUint, + eFormatHex, + {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, exc_fsr}, + nullptr, + nullptr, + }, + {"far", + nullptr, + 4, + EXC_OFFSET(2), + eEncodingUint, + eFormatHex, + {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, exc_far}, + nullptr, + nullptr, }, {DEFINE_DBG(bvr, 0)}, _______________________________________________ lldb-commits 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