mgorny updated this revision to Diff 369415.
mgorny added a comment.
Correct the test case to actually include data for all XMM registers (NFC).
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108468/new/
https://reviews.llvm.org/D108468
Files:
lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
===================================================================
--- /dev/null
+++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -0,0 +1,98 @@
+from __future__ import print_function
+import lldb
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test.decorators import *
+from gdbclientutils import *
+
+
+class TestGDBServerTargetXML(GDBRemoteTestBase):
+
+ @skipIfXmlSupportMissing
+ @skipIfRemote
+ def test_x86_64_vec_regs(self):
+ """Test rendering of x86_64 vector registers from gdbserver."""
+ class MyResponder(MockGDBServerResponder):
+ def qXferRead(self, obj, annex, offset, length):
+ if annex == "target.xml":
+ return """<?xml version="1.0"?>
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <target>
+ <architecture>i386:x86-64</architecture>
+ <osabi>GNU/Linux</osabi>
+ <feature name="org.gnu.gdb.i386.core">
+ <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/>
+ <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/>
+ <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/>
+ <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/>
+ <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/>
+ <reg name="st3" bitsize="80" type="i387_ext" regnum="27"/>
+ <reg name="st4" bitsize="80" type="i387_ext" regnum="28"/>
+ <reg name="st5" bitsize="80" type="i387_ext" regnum="29"/>
+ <reg name="st6" bitsize="80" type="i387_ext" regnum="30"/>
+ <reg name="st7" bitsize="80" type="i387_ext" regnum="31"/>
+ </feature>
+ <feature name="org.gnu.gdb.i386.sse">
+ <reg name="xmm0" bitsize="128" type="vec128" regnum="40"/>
+ <reg name="xmm1" bitsize="128" type="vec128" regnum="41"/>
+ <reg name="xmm2" bitsize="128" type="vec128" regnum="42"/>
+ <reg name="xmm3" bitsize="128" type="vec128" regnum="43"/>
+ <reg name="xmm4" bitsize="128" type="vec128" regnum="44"/>
+ <reg name="xmm5" bitsize="128" type="vec128" regnum="45"/>
+ <reg name="xmm6" bitsize="128" type="vec128" regnum="46"/>
+ <reg name="xmm7" bitsize="128" type="vec128" regnum="47"/>
+ <reg name="xmm8" bitsize="128" type="vec128" regnum="48"/>
+ <reg name="xmm9" bitsize="128" type="vec128" regnum="49"/>
+ <reg name="xmm10" bitsize="128" type="vec128" regnum="50"/>
+ <reg name="xmm11" bitsize="128" type="vec128" regnum="51"/>
+ <reg name="xmm12" bitsize="128" type="vec128" regnum="52"/>
+ <reg name="xmm13" bitsize="128" type="vec128" regnum="53"/>
+ <reg name="xmm14" bitsize="128" type="vec128" regnum="54"/>
+ <reg name="xmm15" bitsize="128" type="vec128" regnum="55"/>
+ <reg name="mxcsr" bitsize="32" type="i386_mxcsr" regnum="56" group="vector"/>
+ </feature>
+ </target>""", False
+ else:
+ return None, False
+
+ def readRegister(self, regnum):
+ return ""
+
+ def readRegisters(self):
+ return (
+ "0102030405060708" # rsp
+ "1112131415161718" # rip
+ "0102030405060708090a" # st0
+ "1112131415161718191a" + # st1
+ "2122232425262728292a" * 6 + # st2..st7
+ "8182838485868788898a8b8c8d8e8f90" # xmm0
+ "9192939495969798999a9b9c9d9e9fa0" # xmm1
+ "a1a2a3a4a5a6a7a8a9aaabacadaeafb0" * 6 # xmm2..xmm7
+ )
+
+ def haltReason(self):
+ return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"
+
+ self.server.responder = MyResponder()
+
+ target = self.createTarget("basic_eh_frame.yaml")
+ process = self.connect(target)
+ lldbutil.expect_state_changes(self, self.dbg.GetListener(), process,
+ [lldb.eStateStopped])
+
+ # rsp and rip should be displayed as uints
+ self.match("register read rsp",
+ ["rsp = 0x0807060504030201"])
+ self.match("register read rip",
+ ["rip = 0x1817161514131211"])
+
+ # both stX and xmmX should be displayed as vectors
+ self.match("register read st0",
+ ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"])
+ self.match("register read st1",
+ ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"])
+ self.match("register read xmm0",
+ ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 "
+ "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"])
+ self.match("register read xmm1",
+ ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 "
+ "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"])
Index: lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
===================================================================
--- lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
+++ lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
@@ -4525,9 +4525,13 @@
} else if (gdb_type == "data_ptr" || gdb_type == "code_ptr") {
reg_info.format = eFormatAddressInfo;
reg_info.encoding = eEncodingUint;
- } else if (gdb_type == "i387_ext" || gdb_type == "float") {
+ } else if (gdb_type == "float") {
reg_info.format = eFormatFloat;
reg_info.encoding = eEncodingIEEE754;
+ } else if (llvm::StringRef(gdb_type).startswith("vec") ||
+ gdb_type == "i387_ext") {
+ reg_info.format = eFormatVectorOfUInt8;
+ reg_info.encoding = eEncodingVector;
}
}
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