Author: Luís Marques Date: 2021-01-07T23:02:55Z New Revision: 15f5971150684b656005cfd5b744c1a34477ff60
URL: https://github.com/llvm/llvm-project/commit/15f5971150684b656005cfd5b744c1a34477ff60 DIFF: https://github.com/llvm/llvm-project/commit/15f5971150684b656005cfd5b744c1a34477ff60.diff LOG: [LLDB][RISCV] Add RISC-V ArchSpec and rv32/rv64 variant detection Adds the RISC-V ArchSpec bits contributed by @simoncook as part of D62732, plus logic to distinguish between riscv32 and riscv64 based on ELF class. The patch follows the implementation approach previously used for MIPS. It defines RISC-V architecture subtypes and inspects the ELF header, namely the ELF class, to detect the right subtype. Differential Revision: https://reviews.llvm.org/D86292 Added: lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml Modified: lldb/include/lldb/Utility/ArchSpec.h lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp lldb/source/Utility/ArchSpec.cpp Removed: ################################################################################ diff --git a/lldb/include/lldb/Utility/ArchSpec.h b/lldb/include/lldb/Utility/ArchSpec.h index a727d5ca4f79..b35766d3d9cf 100644 --- a/lldb/include/lldb/Utility/ArchSpec.h +++ b/lldb/include/lldb/Utility/ArchSpec.h @@ -92,6 +92,12 @@ class ArchSpec { eARM_abi_hard_float = 0x00000400 }; + enum RISCVSubType { + eRISCVSubType_unknown, + eRISCVSubType_riscv32, + eRISCVSubType_riscv64, + }; + enum Core { eCore_arm_generic, eCore_arm_armv4, @@ -184,6 +190,9 @@ class ArchSpec { eCore_hexagon_hexagonv4, eCore_hexagon_hexagonv5, + eCore_riscv32, + eCore_riscv64, + eCore_uknownMach32, eCore_uknownMach64, diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 82a08a235084..cad9ce218b10 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -296,9 +296,23 @@ static uint32_t mipsVariantFromElfFlags (const elf::ELFHeader &header) { return arch_variant; } +static uint32_t riscvVariantFromElfFlags(const elf::ELFHeader &header) { + uint32_t fileclass = header.e_ident[EI_CLASS]; + switch (fileclass) { + case llvm::ELF::ELFCLASS32: + return ArchSpec::eRISCVSubType_riscv32; + case llvm::ELF::ELFCLASS64: + return ArchSpec::eRISCVSubType_riscv64; + default: + return ArchSpec::eRISCVSubType_unknown; + } +} + static uint32_t subTypeFromElfHeader(const elf::ELFHeader &header) { if (header.e_machine == llvm::ELF::EM_MIPS) return mipsVariantFromElfFlags(header); + else if (header.e_machine == llvm::ELF::EM_RISCV) + return riscvVariantFromElfFlags(header); return LLDB_INVALID_CPUTYPE; } diff --git a/lldb/source/Utility/ArchSpec.cpp b/lldb/source/Utility/ArchSpec.cpp index b0cbb269b18b..8025f37c4b38 100644 --- a/lldb/source/Utility/ArchSpec.cpp +++ b/lldb/source/Utility/ArchSpec.cpp @@ -212,6 +212,11 @@ static const CoreDefinition g_core_definitions[] = { {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon, ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"}, + {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32, + "riscv32"}, + {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64, + "riscv64"}, + {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch, ArchSpec::eCore_uknownMach32, "unknown-mach-32"}, {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch, @@ -395,6 +400,10 @@ static const ArchDefinitionEntry g_elf_arch_entries[] = { 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AVR + {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV, + ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32 + {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV, + ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64 }; static const ArchDefinition g_elf_arch_def = { diff --git a/lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml b/lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml new file mode 100644 index 000000000000..7fbf2059c74e --- /dev/null +++ b/lldb/test/Shell/ObjectFile/ELF/riscv-arch.yaml @@ -0,0 +1,24 @@ +# RUN: yaml2obj --docnum=1 %s > %t32 +# RUN: yaml2obj --docnum=2 %s > %t64 +# RUN: lldb-test object-file %t32 | FileCheck --check-prefix=CHECK-RV32 %s +# RUN: lldb-test object-file %t64 | FileCheck --check-prefix=CHECK-RV64 %s + +# CHECK-RV32: Architecture: riscv32-- + +--- !ELF +FileHeader: + Class: ELFCLASS32 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_RISCV +... + +# CHECK-RV64: Architecture: riscv64-- + +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_EXEC + Machine: EM_RISCV +... _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
