omjavaid created this revision.
omjavaid added a reviewer: labath.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
omjavaid requested review of this revision.
This patch removes register set definitions and other redundant code from
NativeRegisterContextLinux/RegisterContextPOSIX*_arm.
Register sets are now moved under RegisterInfosPOSIX_arm which now uses
RegisterInfoAndSetInterface. This is similar to what we earlier did for AArch64.
https://reviews.llvm.org/D86962
Files:
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp
lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
llvm/lib/Transforms/IPO/OpenMPOpt.cpp
Index: llvm/lib/Transforms/IPO/OpenMPOpt.cpp
===================================================================
--- llvm/lib/Transforms/IPO/OpenMPOpt.cpp
+++ llvm/lib/Transforms/IPO/OpenMPOpt.cpp
@@ -407,6 +407,10 @@
return true;
}
+ static const unsigned BasePtrsArgNum = 2;
+ static const unsigned PtrsArgNum = 3;
+ static const unsigned SizesArgNum = 4;
+
private:
/// Traverses the BasicBlock where \p Array is, collecting the stores made to
/// \p Array, leaving StoredValues with the values stored before the
@@ -705,14 +709,12 @@
// offload arrays, offload_baseptrs, offload_ptrs, offload_sizes.
// Therefore:
// i8** %offload_baseptrs.
- const unsigned BasePtrsArgNum = 2;
- Value *BasePtrsArg = RuntimeCall.getArgOperand(BasePtrsArgNum);
+ Value *BasePtrsArg =
+ RuntimeCall.getArgOperand(OffloadArray::BasePtrsArgNum);
// i8** %offload_ptrs.
- const unsigned PtrsArgNum = 3;
- Value *PtrsArg = RuntimeCall.getArgOperand(PtrsArgNum);
+ Value *PtrsArg = RuntimeCall.getArgOperand(OffloadArray::PtrsArgNum);
// i8** %offload_sizes.
- const unsigned SizesArgNum = 4;
- Value *SizesArg = RuntimeCall.getArgOperand(SizesArgNum);
+ Value *SizesArg = RuntimeCall.getArgOperand(OffloadArray::SizesArgNum);
// Get values stored in **offload_baseptrs.
auto *V = getUnderlyingObject(BasePtrsArg);
Index: lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
===================================================================
--- lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
+++ lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
@@ -83,9 +83,6 @@
switch (arch.GetMachine()) {
case llvm::Triple::aarch64:
break;
- case llvm::Triple::arm:
- reg_interface = new RegisterInfoPOSIX_arm(arch);
- break;
case llvm::Triple::ppc:
reg_interface = new RegisterContextFreeBSD_powerpc32(arch);
break;
@@ -122,9 +119,6 @@
case llvm::Triple::Linux: {
switch (arch.GetMachine()) {
- case llvm::Triple::arm:
- reg_interface = new RegisterInfoPOSIX_arm(arch);
- break;
case llvm::Triple::aarch64:
break;
case llvm::Triple::mipsel:
@@ -157,9 +151,6 @@
switch (arch.GetMachine()) {
case llvm::Triple::aarch64:
break;
- case llvm::Triple::arm:
- reg_interface = new RegisterInfoPOSIX_arm(arch);
- break;
case llvm::Triple::x86:
reg_interface = new RegisterContextOpenBSD_i386(arch);
break;
@@ -176,7 +167,8 @@
break;
}
- if (!reg_interface && arch.GetMachine() != llvm::Triple::aarch64) {
+ if (!reg_interface && arch.GetMachine() != llvm::Triple::aarch64 &&
+ arch.GetMachine() != llvm::Triple::arm) {
LLDB_LOGF(log, "elf-core::%s:: Architecture(%d) or OS(%d) not supported",
__FUNCTION__, arch.GetMachine(), arch.GetTriple().getOS());
assert(false && "Architecture or OS not supported");
@@ -190,7 +182,8 @@
break;
case llvm::Triple::arm:
m_thread_reg_ctx_sp = std::make_shared<RegisterContextCorePOSIX_arm>(
- *this, reg_interface, m_gpregset_data, m_notes);
+ *this, std::make_unique<RegisterInfoPOSIX_arm>(arch), m_gpregset_data,
+ m_notes);
break;
case llvm::Triple::mipsel:
case llvm::Triple::mips:
Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
===================================================================
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
@@ -18,7 +18,7 @@
public:
RegisterContextCorePOSIX_arm(
lldb_private::Thread &thread,
- lldb_private::RegisterInfoInterface *register_info,
+ std::unique_ptr<RegisterInfoPOSIX_arm> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
Index: lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
===================================================================
--- lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
+++ lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
@@ -16,9 +16,9 @@
using namespace lldb_private;
RegisterContextCorePOSIX_arm::RegisterContextCorePOSIX_arm(
- Thread &thread, RegisterInfoInterface *register_info,
+ Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
- : RegisterContextPOSIX_arm(thread, 0, register_info) {
+ : RegisterContextPOSIX_arm(thread, std::move(register_info)) {
m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
gpregset.GetByteSize());
m_gpr.SetData(m_gpr_buffer);
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h
@@ -9,12 +9,14 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM_H
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM_H
-#include "RegisterInfoInterface.h"
+#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
-class RegisterInfoPOSIX_arm : public lldb_private::RegisterInfoInterface {
+class RegisterInfoPOSIX_arm : public lldb_private::RegisterInfoAndSetInterface {
public:
+ enum { GPRegSet = 0, FPRegSet, SVERegSet };
+
struct GPR {
uint32_t r[16]; // R0-R15
uint32_t cpsr; // CPSR
@@ -49,10 +51,19 @@
size_t GetGPRSize() const override;
+ size_t GetFPRSize() const override;
+
const lldb_private::RegisterInfo *GetRegisterInfo() const override;
uint32_t GetRegisterCount() const override;
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
private:
const lldb_private::RegisterInfo *m_register_info_p;
uint32_t m_register_info_count;
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp
@@ -71,9 +71,137 @@
}
}
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_cpsr - gpr_r0 + 1,
+ k_num_fpr_registers = fpu_q15 - fpu_s0 + 1,
+ k_num_register_sets = 2
+};
+
+// arm general purpose registers.
+static const uint32_t g_gpr_regnums_arm[] = {
+ gpr_r0,
+ gpr_r1,
+ gpr_r2,
+ gpr_r3,
+ gpr_r4,
+ gpr_r5,
+ gpr_r6,
+ gpr_r7,
+ gpr_r8,
+ gpr_r9,
+ gpr_r10,
+ gpr_r11,
+ gpr_r12,
+ gpr_sp,
+ gpr_lr,
+ gpr_pc,
+ gpr_cpsr,
+ LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
+ k_num_gpr_registers,
+ "g_gpr_regnums_arm has wrong number of register infos");
+
+// arm floating point registers.
+static const uint32_t g_fpu_regnums_arm[] = {
+ fpu_s0,
+ fpu_s1,
+ fpu_s2,
+ fpu_s3,
+ fpu_s4,
+ fpu_s5,
+ fpu_s6,
+ fpu_s7,
+ fpu_s8,
+ fpu_s9,
+ fpu_s10,
+ fpu_s11,
+ fpu_s12,
+ fpu_s13,
+ fpu_s14,
+ fpu_s15,
+ fpu_s16,
+ fpu_s17,
+ fpu_s18,
+ fpu_s19,
+ fpu_s20,
+ fpu_s21,
+ fpu_s22,
+ fpu_s23,
+ fpu_s24,
+ fpu_s25,
+ fpu_s26,
+ fpu_s27,
+ fpu_s28,
+ fpu_s29,
+ fpu_s30,
+ fpu_s31,
+ fpu_fpscr,
+ fpu_d0,
+ fpu_d1,
+ fpu_d2,
+ fpu_d3,
+ fpu_d4,
+ fpu_d5,
+ fpu_d6,
+ fpu_d7,
+ fpu_d8,
+ fpu_d9,
+ fpu_d10,
+ fpu_d11,
+ fpu_d12,
+ fpu_d13,
+ fpu_d14,
+ fpu_d15,
+ fpu_d16,
+ fpu_d17,
+ fpu_d18,
+ fpu_d19,
+ fpu_d20,
+ fpu_d21,
+ fpu_d22,
+ fpu_d23,
+ fpu_d24,
+ fpu_d25,
+ fpu_d26,
+ fpu_d27,
+ fpu_d28,
+ fpu_d29,
+ fpu_d30,
+ fpu_d31,
+ fpu_q0,
+ fpu_q1,
+ fpu_q2,
+ fpu_q3,
+ fpu_q4,
+ fpu_q5,
+ fpu_q6,
+ fpu_q7,
+ fpu_q8,
+ fpu_q9,
+ fpu_q10,
+ fpu_q11,
+ fpu_q12,
+ fpu_q13,
+ fpu_q14,
+ fpu_q15,
+ LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
+ k_num_fpr_registers,
+ "g_fpu_regnums_arm has wrong number of register infos");
+
+// Register sets for arm.
+static const RegisterSet g_reg_sets_arm[k_num_register_sets] = {
+ {"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_arm},
+ {"Floating Point Registers", "fpu", k_num_fpr_registers,
+ g_fpu_regnums_arm}};
+
RegisterInfoPOSIX_arm::RegisterInfoPOSIX_arm(
const lldb_private::ArchSpec &target_arch)
- : lldb_private::RegisterInfoInterface(target_arch),
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
m_register_info_p(GetRegisterInfoPtr(target_arch)),
m_register_info_count(GetRegisterInfoCount(target_arch)) {}
@@ -81,11 +209,35 @@
return sizeof(struct RegisterInfoPOSIX_arm::GPR);
}
+size_t RegisterInfoPOSIX_arm::GetFPRSize() const {
+ return sizeof(struct RegisterInfoPOSIX_arm::FPU);
+}
+
const lldb_private::RegisterInfo *
RegisterInfoPOSIX_arm::GetRegisterInfo() const {
return m_register_info_p;
}
+size_t RegisterInfoPOSIX_arm::GetRegisterSetCount() const {
+ return k_num_register_sets;
+}
+
+size_t RegisterInfoPOSIX_arm::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ if (reg_index <= gpr_cpsr)
+ return GPRegSet;
+ if (reg_index <= fpu_q15)
+ return FPRegSet;
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoPOSIX_arm::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &g_reg_sets_arm[set_index];
+ return nullptr;
+}
+
uint32_t RegisterInfoPOSIX_arm::GetRegisterCount() const {
return m_register_info_count;
}
Index: lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
+++ lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM_H
#include "RegisterInfoInterface.h"
-#include "lldb-arm-register-enums.h"
+#include "RegisterInfoPOSIX_arm.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -18,9 +18,9 @@
class RegisterContextPOSIX_arm : public lldb_private::RegisterContext {
public:
- RegisterContextPOSIX_arm(lldb_private::Thread &thread,
- uint32_t concrete_frame_idx,
- lldb_private::RegisterInfoInterface *register_info);
+ RegisterContextPOSIX_arm(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_arm> register_info);
~RegisterContextPOSIX_arm() override;
@@ -45,46 +45,7 @@
const char *GetRegisterName(unsigned reg);
protected:
- struct RegInfo {
- uint32_t num_registers;
- uint32_t num_gpr_registers;
- uint32_t num_fpr_registers;
-
- uint32_t last_gpr;
- uint32_t first_fpr;
- uint32_t last_fpr;
-
- uint32_t first_fpr_v;
- uint32_t last_fpr_v;
-
- uint32_t gpr_flags;
- };
-
- struct QReg {
- uint8_t bytes[16];
- };
-
- struct FPU {
- union {
- uint32_t s[32];
- uint64_t d[32];
- QReg q[16]; // the 128-bit NEON registers
- } floats;
- uint32_t fpscr;
- };
-
- uint32_t m_gpr_arm[lldb_private::k_num_gpr_registers_arm]; // 32-bit general
- // purpose
- // registers.
- RegInfo m_reg_info;
- struct RegisterContextPOSIX_arm::FPU
- m_fpr; // floating-point registers including extended register sets.
- std::unique_ptr<lldb_private::RegisterInfoInterface>
- m_register_info_up; // Register Info Interface (FreeBSD or Linux)
-
- // Determines if an extended register set is supported on the processor
- // running the inferior process.
- virtual bool IsRegisterSetAvailable(size_t set_index);
+ std::unique_ptr<RegisterInfoPOSIX_arm> m_register_info_up;
virtual const lldb_private::RegisterInfo *GetRegisterInfo();
@@ -92,6 +53,8 @@
bool IsFPR(unsigned reg);
+ size_t GetFPUSize() { return sizeof(RegisterInfoPOSIX_arm::FPU); }
+
virtual bool ReadGPR() = 0;
virtual bool ReadFPR() = 0;
virtual bool WriteGPR() = 0;
Index: lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
@@ -25,88 +25,25 @@
using namespace lldb;
using namespace lldb_private;
-// arm general purpose registers.
-const uint32_t g_gpr_regnums_arm[] = {
- gpr_r0_arm, gpr_r1_arm, gpr_r2_arm, gpr_r3_arm, gpr_r4_arm,
- gpr_r5_arm, gpr_r6_arm, gpr_r7_arm, gpr_r8_arm, gpr_r9_arm,
- gpr_r10_arm, gpr_r11_arm, gpr_r12_arm, gpr_sp_arm, gpr_lr_arm,
- gpr_pc_arm, gpr_cpsr_arm,
- LLDB_INVALID_REGNUM // register sets need to end with this flag
-
-};
-static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
- k_num_gpr_registers_arm,
- "g_gpr_regnums_arm has wrong number of register infos");
-
-// arm floating point registers.
-static const uint32_t g_fpu_regnums_arm[] = {
- fpu_s0_arm, fpu_s1_arm, fpu_s2_arm, fpu_s3_arm, fpu_s4_arm,
- fpu_s5_arm, fpu_s6_arm, fpu_s7_arm, fpu_s8_arm, fpu_s9_arm,
- fpu_s10_arm, fpu_s11_arm, fpu_s12_arm, fpu_s13_arm, fpu_s14_arm,
- fpu_s15_arm, fpu_s16_arm, fpu_s17_arm, fpu_s18_arm, fpu_s19_arm,
- fpu_s20_arm, fpu_s21_arm, fpu_s22_arm, fpu_s23_arm, fpu_s24_arm,
- fpu_s25_arm, fpu_s26_arm, fpu_s27_arm, fpu_s28_arm, fpu_s29_arm,
- fpu_s30_arm, fpu_s31_arm, fpu_fpscr_arm, fpu_d0_arm, fpu_d1_arm,
- fpu_d2_arm, fpu_d3_arm, fpu_d4_arm, fpu_d5_arm, fpu_d6_arm,
- fpu_d7_arm, fpu_d8_arm, fpu_d9_arm, fpu_d10_arm, fpu_d11_arm,
- fpu_d12_arm, fpu_d13_arm, fpu_d14_arm, fpu_d15_arm, fpu_d16_arm,
- fpu_d17_arm, fpu_d18_arm, fpu_d19_arm, fpu_d20_arm, fpu_d21_arm,
- fpu_d22_arm, fpu_d23_arm, fpu_d24_arm, fpu_d25_arm, fpu_d26_arm,
- fpu_d27_arm, fpu_d28_arm, fpu_d29_arm, fpu_d30_arm, fpu_d31_arm,
- fpu_q0_arm, fpu_q1_arm, fpu_q2_arm, fpu_q3_arm, fpu_q4_arm,
- fpu_q5_arm, fpu_q6_arm, fpu_q7_arm, fpu_q8_arm, fpu_q9_arm,
- fpu_q10_arm, fpu_q11_arm, fpu_q12_arm, fpu_q13_arm, fpu_q14_arm,
- fpu_q15_arm,
- LLDB_INVALID_REGNUM // register sets need to end with this flag
-
-};
-static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
- k_num_fpr_registers_arm,
- "g_fpu_regnums_arm has wrong number of register infos");
-
-// Number of register sets provided by this context.
-enum { k_num_register_sets = 2 };
-
-// Register sets for arm.
-static const lldb_private::RegisterSet g_reg_sets_arm[k_num_register_sets] = {
- {"General Purpose Registers", "gpr", k_num_gpr_registers_arm,
- g_gpr_regnums_arm},
- {"Floating Point Registers", "fpu", k_num_fpr_registers_arm,
- g_fpu_regnums_arm}};
-
bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) {
- return reg <= m_reg_info.last_gpr; // GPR's come first.
+ if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_arm::GPRegSet)
+ return true;
+ return false;
}
bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) {
- return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
+ if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_arm::FPRegSet)
+ return true;
+ return false;
}
RegisterContextPOSIX_arm::RegisterContextPOSIX_arm(
- lldb_private::Thread &thread, uint32_t concrete_frame_idx,
- lldb_private::RegisterInfoInterface *register_info)
- : lldb_private::RegisterContext(thread, concrete_frame_idx) {
- m_register_info_up.reset(register_info);
-
- switch (register_info->m_target_arch.GetMachine()) {
- case llvm::Triple::arm:
- m_reg_info.num_registers = k_num_registers_arm;
- m_reg_info.num_gpr_registers = k_num_gpr_registers_arm;
- m_reg_info.num_fpr_registers = k_num_fpr_registers_arm;
- m_reg_info.last_gpr = k_last_gpr_arm;
- m_reg_info.first_fpr = k_first_fpr_arm;
- m_reg_info.last_fpr = k_last_fpr_arm;
- m_reg_info.first_fpr_v = fpu_s0_arm;
- m_reg_info.last_fpr_v = fpu_s31_arm;
- m_reg_info.gpr_flags = gpr_cpsr_arm;
- break;
- default:
- assert(false && "Unhandled target architecture.");
- break;
- }
-
- ::memset(&m_fpr, 0, sizeof m_fpr);
-}
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_arm> register_info)
+ : lldb_private::RegisterContext(thread, 0),
+ m_register_info_up(std::move(register_info)) {}
RegisterContextPOSIX_arm::~RegisterContextPOSIX_arm() {}
@@ -115,19 +52,15 @@
void RegisterContextPOSIX_arm::InvalidateAllRegisters() {}
unsigned RegisterContextPOSIX_arm::GetRegisterOffset(unsigned reg) {
- assert(reg < m_reg_info.num_registers && "Invalid register number.");
- return GetRegisterInfo()[reg].byte_offset;
+ return m_register_info_up->GetRegisterInfo()[reg].byte_offset;
}
unsigned RegisterContextPOSIX_arm::GetRegisterSize(unsigned reg) {
- assert(reg < m_reg_info.num_registers && "Invalid register number.");
- return GetRegisterInfo()[reg].byte_size;
+ return m_register_info_up->GetRegisterInfo()[reg].byte_size;
}
size_t RegisterContextPOSIX_arm::GetRegisterCount() {
- size_t num_registers =
- m_reg_info.num_gpr_registers + m_reg_info.num_fpr_registers;
- return num_registers;
+ return m_register_info_up->GetRegisterCount();
}
size_t RegisterContextPOSIX_arm::GetGPRSize() {
@@ -143,41 +76,23 @@
const lldb_private::RegisterInfo *
RegisterContextPOSIX_arm::GetRegisterInfoAtIndex(size_t reg) {
- if (reg < m_reg_info.num_registers)
+ if (reg < GetRegisterCount())
return &GetRegisterInfo()[reg];
- else
- return nullptr;
+
+ return nullptr;
}
size_t RegisterContextPOSIX_arm::GetRegisterSetCount() {
- size_t sets = 0;
- for (size_t set = 0; set < k_num_register_sets; ++set) {
- if (IsRegisterSetAvailable(set))
- ++sets;
- }
-
- return sets;
+ return m_register_info_up->GetRegisterSetCount();
}
const lldb_private::RegisterSet *
RegisterContextPOSIX_arm::GetRegisterSet(size_t set) {
- if (IsRegisterSetAvailable(set)) {
- switch (m_register_info_up->m_target_arch.GetMachine()) {
- case llvm::Triple::arm:
- return &g_reg_sets_arm[set];
- default:
- assert(false && "Unhandled target architecture.");
- return nullptr;
- }
- }
- return nullptr;
+ return m_register_info_up->GetRegisterSet(set);
}
const char *RegisterContextPOSIX_arm::GetRegisterName(unsigned reg) {
- assert(reg < m_reg_info.num_registers && "Invalid register offset.");
- return GetRegisterInfo()[reg].name;
-}
-
-bool RegisterContextPOSIX_arm::IsRegisterSetAvailable(size_t set_index) {
- return set_index < k_num_register_sets;
+ if (reg < GetRegisterCount())
+ return GetRegisterInfo()[reg].name;
+ return nullptr;
}
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
===================================================================
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
@@ -12,6 +12,7 @@
#define lldb_NativeRegisterContextLinux_arm_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
namespace lldb_private {
@@ -98,37 +99,8 @@
size_t GetFPRSize() override { return sizeof(m_fpr); }
private:
- struct RegInfo {
- uint32_t num_registers;
- uint32_t num_gpr_registers;
- uint32_t num_fpr_registers;
-
- uint32_t last_gpr;
- uint32_t first_fpr;
- uint32_t last_fpr;
-
- uint32_t first_fpr_v;
- uint32_t last_fpr_v;
-
- uint32_t gpr_flags;
- };
-
- struct QReg {
- uint8_t bytes[16];
- };
-
- struct FPU {
- union {
- uint32_t s[32];
- uint64_t d[32];
- QReg q[16]; // the 128-bit NEON registers
- } floats;
- uint32_t fpscr;
- };
-
uint32_t m_gpr_arm[k_num_gpr_registers_arm];
- RegInfo m_reg_info;
- FPU m_fpr;
+ RegisterInfoPOSIX_arm::FPU m_fpr;
// Debug register info for hardware breakpoints and watchpoints management.
struct DREG {
@@ -156,6 +128,8 @@
Status WriteHardwareDebugRegs(int hwbType, int hwb_index);
uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
+
+ RegisterInfoPOSIX_arm &GetRegisterInfo() const;
};
} // namespace process_linux
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
===================================================================
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
@@ -43,55 +43,6 @@
using namespace lldb_private;
using namespace lldb_private::process_linux;
-// arm general purpose registers.
-static const uint32_t g_gpr_regnums_arm[] = {
- gpr_r0_arm, gpr_r1_arm, gpr_r2_arm, gpr_r3_arm, gpr_r4_arm,
- gpr_r5_arm, gpr_r6_arm, gpr_r7_arm, gpr_r8_arm, gpr_r9_arm,
- gpr_r10_arm, gpr_r11_arm, gpr_r12_arm, gpr_sp_arm, gpr_lr_arm,
- gpr_pc_arm, gpr_cpsr_arm,
- LLDB_INVALID_REGNUM // register sets need to end with this flag
-};
-static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
- k_num_gpr_registers_arm,
- "g_gpr_regnums_arm has wrong number of register infos");
-
-// arm floating point registers.
-static const uint32_t g_fpu_regnums_arm[] = {
- fpu_s0_arm, fpu_s1_arm, fpu_s2_arm, fpu_s3_arm, fpu_s4_arm,
- fpu_s5_arm, fpu_s6_arm, fpu_s7_arm, fpu_s8_arm, fpu_s9_arm,
- fpu_s10_arm, fpu_s11_arm, fpu_s12_arm, fpu_s13_arm, fpu_s14_arm,
- fpu_s15_arm, fpu_s16_arm, fpu_s17_arm, fpu_s18_arm, fpu_s19_arm,
- fpu_s20_arm, fpu_s21_arm, fpu_s22_arm, fpu_s23_arm, fpu_s24_arm,
- fpu_s25_arm, fpu_s26_arm, fpu_s27_arm, fpu_s28_arm, fpu_s29_arm,
- fpu_s30_arm, fpu_s31_arm, fpu_fpscr_arm, fpu_d0_arm, fpu_d1_arm,
- fpu_d2_arm, fpu_d3_arm, fpu_d4_arm, fpu_d5_arm, fpu_d6_arm,
- fpu_d7_arm, fpu_d8_arm, fpu_d9_arm, fpu_d10_arm, fpu_d11_arm,
- fpu_d12_arm, fpu_d13_arm, fpu_d14_arm, fpu_d15_arm, fpu_d16_arm,
- fpu_d17_arm, fpu_d18_arm, fpu_d19_arm, fpu_d20_arm, fpu_d21_arm,
- fpu_d22_arm, fpu_d23_arm, fpu_d24_arm, fpu_d25_arm, fpu_d26_arm,
- fpu_d27_arm, fpu_d28_arm, fpu_d29_arm, fpu_d30_arm, fpu_d31_arm,
- fpu_q0_arm, fpu_q1_arm, fpu_q2_arm, fpu_q3_arm, fpu_q4_arm,
- fpu_q5_arm, fpu_q6_arm, fpu_q7_arm, fpu_q8_arm, fpu_q9_arm,
- fpu_q10_arm, fpu_q11_arm, fpu_q12_arm, fpu_q13_arm, fpu_q14_arm,
- fpu_q15_arm,
- LLDB_INVALID_REGNUM // register sets need to end with this flag
-};
-static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
- k_num_fpr_registers_arm,
- "g_fpu_regnums_arm has wrong number of register infos");
-
-namespace {
-// Number of register sets provided by this context.
-enum { k_num_register_sets = 2 };
-}
-
-// Register sets for arm.
-static const RegisterSet g_reg_sets_arm[k_num_register_sets] = {
- {"General Purpose Registers", "gpr", k_num_gpr_registers_arm,
- g_gpr_regnums_arm},
- {"Floating Point Registers", "fpu", k_num_fpr_registers_arm,
- g_fpu_regnums_arm}};
-
#if defined(__arm__)
std::unique_ptr<NativeRegisterContextLinux>
@@ -109,49 +60,41 @@
new RegisterInfoPOSIX_arm(target_arch)) {
switch (target_arch.GetMachine()) {
case llvm::Triple::arm:
- m_reg_info.num_registers = k_num_registers_arm;
- m_reg_info.num_gpr_registers = k_num_gpr_registers_arm;
- m_reg_info.num_fpr_registers = k_num_fpr_registers_arm;
- m_reg_info.last_gpr = k_last_gpr_arm;
- m_reg_info.first_fpr = k_first_fpr_arm;
- m_reg_info.last_fpr = k_last_fpr_arm;
- m_reg_info.first_fpr_v = fpu_s0_arm;
- m_reg_info.last_fpr_v = fpu_s31_arm;
- m_reg_info.gpr_flags = gpr_cpsr_arm;
+ ::memset(&m_fpr, 0, sizeof(m_fpr));
+ ::memset(&m_gpr_arm, 0, sizeof(m_gpr_arm));
+ ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
+ ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
+
+ // 16 is just a maximum value, query hardware for actual watchpoint count
+ m_max_hwp_supported = 16;
+ m_max_hbp_supported = 16;
+ m_refresh_hwdebug_info = true;
+
break;
default:
assert(false && "Unhandled target architecture.");
break;
}
+}
- ::memset(&m_fpr, 0, sizeof(m_fpr));
- ::memset(&m_gpr_arm, 0, sizeof(m_gpr_arm));
- ::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
- ::memset(&m_hbr_regs, 0, sizeof(m_hbr_regs));
-
- // 16 is just a maximum value, query hardware for actual watchpoint count
- m_max_hwp_supported = 16;
- m_max_hbp_supported = 16;
- m_refresh_hwdebug_info = true;
+RegisterInfoPOSIX_arm &NativeRegisterContextLinux_arm::GetRegisterInfo() const {
+ return static_cast<RegisterInfoPOSIX_arm &>(*m_register_info_interface_up);
}
uint32_t NativeRegisterContextLinux_arm::GetRegisterSetCount() const {
- return k_num_register_sets;
+ return GetRegisterInfo().GetRegisterSetCount();
}
uint32_t NativeRegisterContextLinux_arm::GetUserRegisterCount() const {
uint32_t count = 0;
- for (uint32_t set_index = 0; set_index < k_num_register_sets; ++set_index)
- count += g_reg_sets_arm[set_index].num_registers;
+ for (uint32_t set_index = 0; set_index < GetRegisterSetCount(); ++set_index)
+ count += GetRegisterSet(set_index)->num_registers;
return count;
}
const RegisterSet *
NativeRegisterContextLinux_arm::GetRegisterSet(uint32_t set_index) const {
- if (set_index < k_num_register_sets)
- return &g_reg_sets_arm[set_index];
-
- return nullptr;
+ return GetRegisterInfo().GetRegisterSet(set_index);
}
Status
@@ -336,11 +279,17 @@
}
bool NativeRegisterContextLinux_arm::IsGPR(unsigned reg) const {
- return reg <= m_reg_info.last_gpr; // GPR's come first.
+ if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_arm::GPRegSet)
+ return true;
+ return false;
}
bool NativeRegisterContextLinux_arm::IsFPR(unsigned reg) const {
- return (m_reg_info.first_fpr <= reg && reg <= m_reg_info.last_fpr);
+ if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_arm::FPRegSet)
+ return true;
+ return false;
}
uint32_t NativeRegisterContextLinux_arm::NumSupportedHardwareBreakpoints() {
@@ -851,8 +800,7 @@
uint32_t NativeRegisterContextLinux_arm::CalculateFprOffset(
const RegisterInfo *reg_info) const {
- return reg_info->byte_offset -
- GetRegisterInfoAtIndex(m_reg_info.first_fpr)->byte_offset;
+ return reg_info->byte_offset - GetGPRSize();
}
Status NativeRegisterContextLinux_arm::DoReadRegisterValue(
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