dstenb added a comment. In D73534#1881353 <https://reviews.llvm.org/D73534#1881353>, @nickdesaulniers wrote:
> As a heads up, Linaro's ToolChain Working Group's Linux kernel CI lit up on > this change. I see it's been reverted (thank you). Please cc me on the > updated patch and I can help test it against the Linux kernel. > > Edit: Link: > https://ci.linaro.org/job/tcwg_kernel-bisect-llvm-master-arm-mainline-allyesconfig/25/artifact/artifacts/build-a82d3e8a6e67473c94a5ce6345372748e9b61718/03-build_linux/console.log Its hard to tell from the backtrace, but looking at the code, I think this might be a bug that sneaked in when I did D70431 <https://reviews.llvm.org/D70431>. Sorry if that is the case! `ARMBaseInstrInfo::isAddImmediate()` does a `getReg()` without any `isReg()` guard: Optional<RegImmPair> ARMBaseInstrInfo::isAddImmediate(const MachineInstr &MI, Register Reg) const { [...] // TODO: Handle cases where Reg is a super- or sub-register of the // destination register. if (Reg != MI.getOperand(0).getReg()) return None; CHANGES SINCE LAST ACTION https://reviews.llvm.org/D73534/new/ https://reviews.llvm.org/D73534 _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
