https://github.com/barsolo2000 updated https://github.com/llvm/llvm-project/pull/165796
>From 7ad2138ab6a9e61b84575f4f41762778cc7e0ad4 Mon Sep 17 00:00:00 2001 From: Bar Soloveychik <[email protected]> Date: Thu, 30 Oct 2025 16:07:24 -0700 Subject: [PATCH] Adding vlenb register as callee register --- lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp index b313ca03fb970..d46593358ba6d 100644 --- a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp +++ b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp @@ -798,6 +798,8 @@ bool ABISysV_riscv::RegisterIsCalleeSaved(const RegisterInfo *reg_info) { // floating point hardware names .Cases("f8", "f9", "f18", "f19", "f20", "f21", "f22", "f23", is_hw_fp) .Cases("f24", "f25", "f26", "f27", is_hw_fp) + // vlenb is constant and needed for vector unwinding. + .Case("vlenb", true) .Default(false); return is_callee_saved; _______________________________________________ lldb-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
