================
@@ -242,9 +278,35 @@ Store(EmulateInstructionRISCV &emulator, I inst) {
auto addr = LoadStoreAddr(emulator, inst);
if (!addr)
return false;
- return transformOptional(
- inst.rs2.Read(emulator),
- [&](uint64_t rs2) { return emulator.WriteMem<T>(*addr, rs2); })
+
+ // Set up context for the store operation, similar to ARM64
+ EmulateInstructionRISCV::Context context;
+
+ // Get register info for source and base registers
+ std::optional<RegisterInfo> reg_info_rs1 =
+ GPREncodingToRegisterInfo(emulator, inst.rs1.rs);
+ std::optional<RegisterInfo> reg_info_rs2 =
+ GPREncodingToRegisterInfo(emulator, inst.rs2.rs);
+
+ if (!reg_info_rs1 || !reg_info_rs2)
+ return false;
+
+ // Set context type based on whether this is a stack-based store
+ if (inst.rs1.rs == RISCV_GPR_SP) // x2 is the stack pointer in RISC-V
----------------
clayborg wrote:
We probably don't need this comment now that we are using `RISCV_GPR_SP`?
https://github.com/llvm/llvm-project/pull/158161
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