Author: Roman Date: 2025-08-30T13:41:25Z New Revision: 912ce2631ff397660236a7dc35247f390b1d7818
URL: https://github.com/llvm/llvm-project/commit/912ce2631ff397660236a7dc35247f390b1d7818 DIFF: https://github.com/llvm/llvm-project/commit/912ce2631ff397660236a7dc35247f390b1d7818.diff LOG: [NFC] Fix typos 'seperate' -> 'separate' (#144368) Correct few typos: 'seperate' -> 'separate' . Added: Modified: clang/test/AST/HLSL/RootSignatures-AST.hlsl clang/test/Modules/safe_buffers_optout.cpp lldb/include/lldb/Target/CoreFileMemoryRanges.h llvm/include/llvm/Analysis/VectorUtils.h llvm/lib/IR/DebugInfo.cpp llvm/lib/Transforms/Utils/IRNormalizer.cpp mlir/lib/Bindings/Python/IRAttributes.cpp mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir mlir/tools/mlir-tblgen/EnumsGen.cpp Removed: ################################################################################ diff --git a/clang/test/AST/HLSL/RootSignatures-AST.hlsl b/clang/test/AST/HLSL/RootSignatures-AST.hlsl index df06165f1f1f9..32da1f14853b0 100644 --- a/clang/test/AST/HLSL/RootSignatures-AST.hlsl +++ b/clang/test/AST/HLSL/RootSignatures-AST.hlsl @@ -115,7 +115,7 @@ void same_rs_string_main() {} "DescriptorTable(Sampler(s0, numDescriptors = 4, space = 1))" // Ensure that when we define a diff erent type root signature that it creates -// a seperate decl and identifier to reference +// a separate decl and identifier to reference // CHECK: -HLSLRootSignatureDecl 0x{{.*}} {{.*}} implicit [[DIFF_RS_DECL:__hlsl_rootsig_decl_\d*]] // CHECK-V1_0: version: 1.0, diff --git a/clang/test/Modules/safe_buffers_optout.cpp b/clang/test/Modules/safe_buffers_optout.cpp index 8c3d6a235d399..39020a48925e1 100644 --- a/clang/test/Modules/safe_buffers_optout.cpp +++ b/clang/test/Modules/safe_buffers_optout.cpp @@ -96,7 +96,7 @@ int textual(int *p) { // `safe_buffers_test_base`. (So the module dependencies form a DAG.) // No expected warnings from base.h, test_sub1, or test_sub2 because they are -// in seperate modules, and the explicit commands that builds them have no +// in separate modules, and the explicit commands that builds them have no // `-Wunsafe-buffer-usage`. int foo(int * p) { @@ -122,7 +122,7 @@ int foo(int * p) { // `safe_buffers_test_base`. (So the module dependencies form a DAG.) // No expected warnings from base.h, test_sub1, or test_sub2 because they are -// in seperate modules, and the explicit commands that builds them have no +// in separate modules, and the explicit commands that builds them have no // `-Wunsafe-buffer-usage`. int foo(int * p) { diff --git a/lldb/include/lldb/Target/CoreFileMemoryRanges.h b/lldb/include/lldb/Target/CoreFileMemoryRanges.h index 78d01acca324e..ef56a02ddee27 100644 --- a/lldb/include/lldb/Target/CoreFileMemoryRanges.h +++ b/lldb/include/lldb/Target/CoreFileMemoryRanges.h @@ -50,7 +50,7 @@ class CoreFileMemoryRanges CoreFileMemoryRange> { public: /// Finalize and merge all overlapping ranges in this collection. Ranges - /// will be seperated based on permissions. + /// will be separated based on permissions. Status FinalizeCoreFileSaveRanges(); }; } // namespace lldb_private diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h index 6781cd5c606e9..ce94906ee7c00 100644 --- a/llvm/include/llvm/Analysis/VectorUtils.h +++ b/llvm/include/llvm/Analysis/VectorUtils.h @@ -145,7 +145,7 @@ LLVM_ABI bool isTriviallyVectorizable(Intrinsic::ID ID); /// Note: There are intrinsics where implementing vectorization for the /// intrinsic is redundant, but we want to implement scalarization of the /// vector. To prevent the requirement that an intrinsic also implements -/// vectorization we provide this seperate function. +/// vectorization we provide this separate function. LLVM_ABI bool isTriviallyScalarizable(Intrinsic::ID ID, const TargetTransformInfo *TTI); diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index 8e523bcf7960e..b468d929b0280 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -755,7 +755,7 @@ class DebugTypeInfoRemoval { return getReplacementMDNode(N); }; - // Seperate recursive doRemap and operator [] into 2 lines to avoid + // Separate recursive doRemap and operator [] into 2 lines to avoid // out-of-order evaluations since both of them can access the same memory // location in map Replacements. auto Value = doRemap(N); diff --git a/llvm/lib/Transforms/Utils/IRNormalizer.cpp b/llvm/lib/Transforms/Utils/IRNormalizer.cpp index ad91318ae474c..fefa49f68c8da 100644 --- a/llvm/lib/Transforms/Utils/IRNormalizer.cpp +++ b/llvm/lib/Transforms/Utils/IRNormalizer.cpp @@ -427,7 +427,7 @@ void IRNormalizer::reorderInstructions(Function &F) const { // Process the remaining instructions. // // TODO: Do more a intelligent sorting of these instructions. For example, - // seperate between dead instructinos and instructions used in another + // separate between dead instructinos and instructions used in another // block. Use properties of the CFG the order instructions that are used // in another block. if (Visited.contains(&I)) diff --git a/mlir/lib/Bindings/Python/IRAttributes.cpp b/mlir/lib/Bindings/Python/IRAttributes.cpp index af950ce8114fb..f2eafa7c2d45c 100644 --- a/mlir/lib/Bindings/Python/IRAttributes.cpp +++ b/mlir/lib/Bindings/Python/IRAttributes.cpp @@ -1125,7 +1125,7 @@ class PyDenseElementsAttribute bulkLoadElementType = mlirF16TypeGet(context); } else if (format == "?") { // i1 - // The i1 type needs to be bit-packed, so we will handle it seperately + // The i1 type needs to be bit-packed, so we will handle it separately return getBitpackedAttributeFromBooleanBuffer(view, explicitShape, context); } else if (isSignedIntegerFormat(format)) { diff --git a/mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir b/mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir index 0bf38ba5947c0..3b51e6b1e1b6f 100644 --- a/mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir +++ b/mlir/test/Dialect/Vector/vector-reduce-to-contract.mlir @@ -1,6 +1,6 @@ // RUN: mlir-opt %s -test-vector-reduction-to-contract-patterns -split-input-file | FileCheck %s -// TODO: Seperate tests for vector.multi_reduction -> vector.contract and +// TODO: Separate tests for vector.multi_reduction -> vector.contract and // * pre-op + vector.contract -> vector.contract, // * vector.contract + post-op -> vector.contract. diff --git a/mlir/tools/mlir-tblgen/EnumsGen.cpp b/mlir/tools/mlir-tblgen/EnumsGen.cpp index 06dc588f90203..d152763f7382e 100644 --- a/mlir/tools/mlir-tblgen/EnumsGen.cpp +++ b/mlir/tools/mlir-tblgen/EnumsGen.cpp @@ -222,7 +222,7 @@ inline ::llvm::raw_ostream &operator<<(::llvm::raw_ostream &p, {0} value) {{ llvm::StringSwitch<StringRef>(separator.trim()) .Case("|", "parseOptionalVerticalBar") .Case(",", "parseOptionalComma") - .Default("error, enum seperator must be '|' or ','"); + .Default("error, enum separator must be '|' or ','"); os << formatv(parsedAndPrinterStartUnquotedBitEnum, qualName, cppNamespace, enumInfo.getSummary(), casesList, separator, parseSeparatorFn); _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
