Author: David Spickett Date: 2025-03-10T10:10:19Z New Revision: fe544d404d841ef44aebf4fc36948fd1e1d89685
URL: https://github.com/llvm/llvm-project/commit/fe544d404d841ef44aebf4fc36948fd1e1d89685 DIFF: https://github.com/llvm/llvm-project/commit/fe544d404d841ef44aebf4fc36948fd1e1d89685.diff LOG: [lldb] Add more ARM checks in TestLldbGdbServer.py (#130277) When https://github.com/llvm/llvm-project/pull/130034 enabled RISC-V here I noticed that these should run for ARM as well. ARM only has 4 argument registers, which matches Arm's ABI for it: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#core-registers The ABI defines a link register LR, and I assume that's what becomes 'ra' in LLDB. Tested on ARM and AArch64 Linux. Added: Modified: lldb/packages/Python/lldbsuite/test/lldbtest.py lldb/test/API/tools/lldb-server/TestLldbGdbServer.py Removed: ################################################################################ diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py index 7d0e6e9a970eb..590024ef77119 100644 --- a/lldb/packages/Python/lldbsuite/test/lldbtest.py +++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py @@ -1344,6 +1344,13 @@ def isAArch64(self): arch = self.getArchitecture().lower() return arch in ["aarch64", "arm64", "arm64e"] + def isARM(self): + """Returns true if the architecture is ARM, meaning 32-bit ARM. Which could + be M profile, A profile Armv7-a, or the AArch32 mode of Armv8-a.""" + return not self.isAArch64() and ( + self.getArchitecture().lower().startswith("arm") + ) + def isAArch64SVE(self): return self.isAArch64() and "sve" in self.getCPUInfo() diff --git a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py index ce75e3e89e0a6..12c97bc62dcef 100644 --- a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py +++ b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py @@ -199,12 +199,12 @@ def test_qRegisterInfo_contains_required_generics_debugserver(self): if not self.isRISCV(): self.assertIn("flags", generic_regs) - if self.isRISCV(): - # Special RISC-V register for a return address + if self.isRISCV() or self.isAArch64() or self.isARM(): + # Specific register for a return address self.assertIn("ra", generic_regs) - # RISC-V's function arguments registers - for i in range(1, 9): + # Function arguments registers + for i in range(1, 5 if self.isARM() else 9): self.assertIn(f"arg{i}", generic_regs) def test_qRegisterInfo_contains_at_least_one_register_set(self): _______________________________________________ lldb-commits mailing list lldb-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
