https://github.com/wangleiat updated
https://github.com/llvm/llvm-project/pull/124059
>From f4777704df6b2ac7b7ab33e3baadd3830154904a Mon Sep 17 00:00:00 2001
From: Ray Wang <wangray1...@gmail.com>
Date: Thu, 23 Jan 2025 12:13:32 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=?UTF-8?q?itial=20version?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Created using spr 1.3.5-bogner
---
.../ABI/LoongArch/ABISysV_loongarch.cpp | 38 +++++++------------
1 file changed, 14 insertions(+), 24 deletions(-)
diff --git a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
index dc7e9bba000676d..272c6a6be529ff3 100644
--- a/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
+++ b/lldb/source/Plugins/ABI/LoongArch/ABISysV_loongarch.cpp
@@ -644,32 +644,22 @@ void ABISysV_loongarch::AugmentRegisterInfo(
std::vector<lldb_private::DynamicRegisterInfo::Register> ®s) {
lldb_private::RegInfoBasedABI::AugmentRegisterInfo(regs);
+ static const std::unordered_map<std::string, std::string> reg_aliases = {
+ {"r0", "zero"}, {"r1", "ra"}, {"r2", "tp"}, {"r3", "sp"},
+ {"r4", "a0"}, {"r5", "a1"}, {"r6", "a2"}, {"r7", "a3"},
+ {"r8", "a4"}, {"r9", "a5"}, {"r10", "a6"}, {"r11", "a7"},
+ {"r12", "t0"}, {"r13", "t1"}, {"r14", "t2"}, {"r15", "t3"},
+ {"r16", "t4"}, {"r17", "t5"}, {"r18", "t6"}, {"r19", "t7"},
+ {"r20", "t8"}, {"r22", "fp"}, {"r23", "s0"}, {"r24", "s1"},
+ {"r25", "s2"}, {"r26", "s3"}, {"r27", "s4"}, {"r28", "s5"},
+ {"r29", "s6"}, {"r30", "s7"}, {"r31", "s8"}};
+
for (auto it : llvm::enumerate(regs)) {
// Set alt name for certain registers for convenience
- if (it.value().name == "r0")
- it.value().alt_name.SetCString("zero");
- else if (it.value().name == "r1")
- it.value().alt_name.SetCString("ra");
- else if (it.value().name == "r3")
- it.value().alt_name.SetCString("sp");
- else if (it.value().name == "r22")
- it.value().alt_name.SetCString("fp");
- else if (it.value().name == "r4")
- it.value().alt_name.SetCString("a0");
- else if (it.value().name == "r5")
- it.value().alt_name.SetCString("a1");
- else if (it.value().name == "r6")
- it.value().alt_name.SetCString("a2");
- else if (it.value().name == "r7")
- it.value().alt_name.SetCString("a3");
- else if (it.value().name == "r8")
- it.value().alt_name.SetCString("a4");
- else if (it.value().name == "r9")
- it.value().alt_name.SetCString("a5");
- else if (it.value().name == "r10")
- it.value().alt_name.SetCString("a6");
- else if (it.value().name == "r11")
- it.value().alt_name.SetCString("a7");
+ std::string reg_name = it.value().name.GetStringRef().str();
+ if (auto alias = reg_aliases.find(reg_name); alias != reg_aliases.end()) {
+ it.value().alt_name.SetCString(alias->second.c_str());
+ }
// Set generic regnum so lldb knows what the PC, etc is
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
>From d03f4f2b191c09d6492249aa5e0d50fc62a5a434 Mon Sep 17 00:00:00 2001
From: Ray Wang <wangray1...@gmail.com>
Date: Wed, 5 Feb 2025 17:58:09 +0800
Subject: [PATCH 2/2] add test
Created using spr 1.3.5-bogner
---
.../postmortem/elf-core/TestLinuxCore.py | 82 ++++++++++---------
1 file changed, 44 insertions(+), 38 deletions(-)
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 376d6492d83b604..adabac106f3e375 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -642,8 +642,7 @@ def test_aarch64_sve_regs_full(self):
)
# RMode should have enumerator descriptions.
self.expect(
- "register info fpcr",
- substrs=["RMode: 0 = RN, 1 = RP, 2 = RM, 3 = RZ"],
+ "register info fpcr", substrs=["RMode: 0 = RN, 1 = RP, 2 = RM, 3 =
RZ"]
)
@skipIfLLVMTargetMissing("AArch64")
@@ -852,41 +851,42 @@ def test_loongarch64_regs(self):
self.assertTrue(target, VALID_TARGET)
process = target.LoadCore("linux-loongarch64.core")
- values = {}
- values["r0"] = "0x0000000000000000"
- values["r1"] = "0x000000012000016c"
- values["r2"] = "0x0000000000000000"
- values["r3"] = "0x00007ffffb8249e0"
- values["r4"] = "0x0000000000000000"
- values["r5"] = "0x000000012000010c"
- values["r6"] = "0x0000000000000000"
- values["r7"] = "0x0000000000000000"
- values["r8"] = "0x0000000000000000"
- values["r9"] = "0x0000000000000000"
- values["r10"] = "0x0000000000000000"
- values["r11"] = "0x00000000000000dd"
- values["r12"] = "0x0000000000000000"
- values["r13"] = "0x000000000000002f"
- values["r14"] = "0x0000000000000000"
- values["r15"] = "0x0000000000000000"
- values["r16"] = "0x0000000000000000"
- values["r17"] = "0x0000000000000000"
- values["r18"] = "0x0000000000000000"
- values["r19"] = "0x0000000000000000"
- values["r20"] = "0x0000000000000000"
- values["r21"] = "0x0000000000000000"
- values["r22"] = "0x00007ffffb824a10"
- values["r23"] = "0x0000000000000000"
- values["r24"] = "0x0000000000000000"
- values["r25"] = "0x0000000000000000"
- values["r26"] = "0x0000000000000000"
- values["r27"] = "0x0000000000000000"
- values["r28"] = "0x0000000000000000"
- values["r29"] = "0x0000000000000000"
- values["r30"] = "0x0000000000000000"
- values["r31"] = "0x0000000000000000"
- values["orig_a0"] = "0x0000555556b62d50"
- values["pc"] = "0x000000012000012c"
+ values = {
+ "r0": ("0x0000000000000000", "zero"),
+ "r1": ("0x000000012000016c", "ra"),
+ "r2": ("0x0000000000000000", "tp"),
+ "r3": ("0x00007ffffb8249e0", "sp"),
+ "r4": ("0x0000000000000000", "a0"),
+ "r5": ("0x000000012000010c", "a1"),
+ "r6": ("0x0000000000000000", "a2"),
+ "r7": ("0x0000000000000000", "a3"),
+ "r8": ("0x0000000000000000", "a4"),
+ "r9": ("0x0000000000000000", "a5"),
+ "r10": ("0x0000000000000000", "a6"),
+ "r11": ("0x00000000000000dd", "a7"),
+ "r12": ("0x0000000000000000", "t0"),
+ "r13": ("0x000000000000002f", "t1"),
+ "r14": ("0x0000000000000000", "t2"),
+ "r15": ("0x0000000000000000", "t3"),
+ "r16": ("0x0000000000000000", "t4"),
+ "r17": ("0x0000000000000000", "t5"),
+ "r18": ("0x0000000000000000", "t6"),
+ "r19": ("0x0000000000000000", "t7"),
+ "r20": ("0x0000000000000000", "t8"),
+ "r21": ("0x0000000000000000", None),
+ "r22": ("0x00007ffffb824a10", "fp"),
+ "r23": ("0x0000000000000000", "s0"),
+ "r24": ("0x0000000000000000", "s1"),
+ "r25": ("0x0000000000000000", "s2"),
+ "r26": ("0x0000000000000000", "s3"),
+ "r27": ("0x0000000000000000", "s4"),
+ "r28": ("0x0000000000000000", "s5"),
+ "r29": ("0x0000000000000000", "s6"),
+ "r30": ("0x0000000000000000", "s7"),
+ "r31": ("0x0000000000000000", "s8"),
+ "orig_a0": ("0x0000555556b62d50", None),
+ "pc": ("0x000000012000012c", None),
+ }
fpr_values = {}
fpr_values["f0"] = "0x00000000ffffff05"
@@ -931,11 +931,17 @@ def test_loongarch64_regs(self):
fpr_values["fcc7"] = "0x01"
fpr_values["fcsr"] = "0x00000000"
- for regname, value in values.items():
+ for regname in values:
+ value, alias = values[regname]
self.expect(
"register read {}".format(regname),
substrs=["{} = {}".format(regname, value)],
)
+ if alias:
+ self.expect(
+ "register read {}".format(alias),
+ substrs=["{} = {}".format(regname, value)],
+ )
for regname, value in fpr_values.items():
self.expect(
_______________________________________________
lldb-commits mailing list
lldb-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/lldb-commits
