https://github.com/kper updated https://github.com/llvm/llvm-project/pull/124475
>From 096eb85718d70721cec1e539cfa4b05a96475c7a Mon Sep 17 00:00:00 2001
From: Kevin Per <kevin....@protonmail.com>
Date: Sun, 26 Jan 2025 17:34:17 +0000
Subject: [PATCH 1/3] lldb: Extended if conditions to support alias names for
registers
---
.../Plugins/ABI/RISCV/ABISysV_riscv.cpp | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
index 8412991933d277..c463bd006b3db4 100644
--- a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
+++ b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
@@ -850,8 +850,62 @@ void ABISysV_riscv::AugmentRegisterInfo(
it.value().alt_name.SetCString("x3");
else if (it.value().name == "fp")
it.value().alt_name.SetCString("s0");
+ else if (it.value().name == "tp")
+ it.value().alt_name.SetCString("x4");
else if (it.value().name == "s0")
it.value().alt_name.SetCString("x8");
+ else if (it.value().name == "s1")
+ it.value().alt_name.SetCString("x9");
+ else if (it.value().name == "t0")
+ it.value().alt_name.SetCString("x5");
+ else if (it.value().name == "t1")
+ it.value().alt_name.SetCString("x6");
+ else if (it.value().name == "t2")
+ it.value().alt_name.SetCString("x7");
+ else if (it.value().name == "a0")
+ it.value().alt_name.SetCString("x10");
+ else if (it.value().name == "a1")
+ it.value().alt_name.SetCString("x11");
+ else if (it.value().name == "a2")
+ it.value().alt_name.SetCString("x12");
+ else if (it.value().name == "a3")
+ it.value().alt_name.SetCString("x13");
+ else if (it.value().name == "a4")
+ it.value().alt_name.SetCString("x14");
+ else if (it.value().name == "a5")
+ it.value().alt_name.SetCString("x15");
+ else if (it.value().name == "a6")
+ it.value().alt_name.SetCString("x16");
+ else if (it.value().name == "a7")
+ it.value().alt_name.SetCString("x17");
+ else if (it.value().name == "s2")
+ it.value().alt_name.SetCString("x18");
+ else if (it.value().name == "s3")
+ it.value().alt_name.SetCString("x19");
+ else if (it.value().name == "s4")
+ it.value().alt_name.SetCString("x20");
+ else if (it.value().name == "s5")
+ it.value().alt_name.SetCString("x21");
+ else if (it.value().name == "s6")
+ it.value().alt_name.SetCString("x22");
+ else if (it.value().name == "s7")
+ it.value().alt_name.SetCString("x23");
+ else if (it.value().name == "s8")
+ it.value().alt_name.SetCString("x24");
+ else if (it.value().name == "s9")
+ it.value().alt_name.SetCString("x25");
+ else if (it.value().name == "s10")
+ it.value().alt_name.SetCString("x26");
+ else if (it.value().name == "s11")
+ it.value().alt_name.SetCString("x27");
+ else if (it.value().name == "t3")
+ it.value().alt_name.SetCString("x28");
+ else if (it.value().name == "t4")
+ it.value().alt_name.SetCString("x29");
+ else if (it.value().name == "t5")
+ it.value().alt_name.SetCString("x30");
+ else if (it.value().name == "t6")
+ it.value().alt_name.SetCString("x31");
// Set generic regnum so lldb knows what the PC, etc is
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
>From ad3dfa270953a04f755773c402941fd10165a098 Mon Sep 17 00:00:00 2001
From: Kevin Per <kevin....@protonmail.com>
Date: Tue, 28 Jan 2025 15:23:54 +0000
Subject: [PATCH 2/3] Added RISCV reg test for the ServerTargetXML
---
.../TestGDBServerTargetXML.py | 149 ++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git
a/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
b/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
index 22f5553e40802d..c74726a88aa6ff 100644
--- a/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ b/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -652,6 +652,155 @@ def haltReason(self):
)
self.match("register read s31", ["s31 = 128"])
+ @skipIfXmlSupportMissing
+ @skipIfRemote
+ @skipIfLLVMTargetMissing("RISCV")
+ def test_riscv64_regs(self):
+ """Test grabbing various riscv64 registers from gdbserver."""
+
+ class MyResponder(MockGDBServerResponder):
+ reg_data = (
+ (
+ "0102030405060708" # zero
+ "0102030405060708" # ra
+ "0102030405060708" # sp
+ "0102030405060708" # gp
+ "0102030405060708" # tp
+ "0102030405060708" # t0
+ "0102030405060708" # t1
+ "0102030405060708" # t2
+ "0102030405060708" # fp
+ "0102030405060708" # s1
+ "0102030405060708" # a0
+ "0102030405060708" # a1
+ "0102030405060708" # a2
+ "0102030405060708" # a3
+ "0102030405060708" # a4
+ "0102030405060708" # a5
+ "0102030405060708" # a6
+ "0102030405060708" # a7
+ "0102030405060708" # s2
+ "0102030405060708" # s3
+ "0102030405060708" # s4
+ "0102030405060708" # s5
+ "0102030405060708" # s6
+ "0102030405060708" # s7
+ "0102030405060708" # s8
+ "0102030405060708" # s9
+ "0102030405060708" # s10
+ "0102030405060708" # s11
+ "0102030405060708" # t3
+ "0102030405060708" # t4
+ "0102030405060708" # t5
+ "0102030405060708" # t6
+ )
+ )
+
+ def qXferRead(self, obj, annex, offset, length):
+ if annex == "target.xml":
+ return (
+ """<?xml version="1.0"?>
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ </feature>
+ </target>""",
+ False,
+ )
+ else:
+ return None, False
+
+ def readRegister(self, regnum):
+ return ""
+
+ def readRegisters(self):
+ return self.reg_data
+
+ def writeRegisters(self, reg_hex):
+ self.reg_data = reg_hex
+ return "OK"
+
+ def haltReason(self):
+ return
"T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"
+
+ self.server.responder = MyResponder()
+
+ target = self.createTarget("basic_eh_frame-riscv64.yaml")
+ process = self.connect(target)
+ lldbutil.expect_state_changes(
+ self, self.dbg.GetListener(), process, [lldb.eStateStopped]
+ )
+
+ # test generic aliases
+ self.match("register read x0", ["zero = 0x0807060504030201"])
+ self.match("register read x1", ["ra = 0x0807060504030201"])
+ self.match("register read x2", ["sp = 0x0807060504030201"])
+ self.match("register read x3", ["gp = 0x0807060504030201"])
+ self.match("register read x4", ["tp = 0x0807060504030201"])
+ self.match("register read x5", ["t0 = 0x0807060504030201"])
+ self.match("register read x6", ["t1 = 0x0807060504030201"])
+ self.match("register read x7", ["t2 = 0x0807060504030201"])
+ # Register x8 is probably not working because it has two aliases fp, s0
+ # self.match("register read x8", ["fp = 0x0807060504030201"])
+ self.match("register read x9", ["s1 = 0x0807060504030201"])
+ self.match("register read x10", ["a0 = 0x0807060504030201"])
+ self.match("register read x11", ["a1 = 0x0807060504030201"])
+ self.match("register read x12", ["a2 = 0x0807060504030201"])
+ self.match("register read x13", ["a3 = 0x0807060504030201"])
+ self.match("register read x14", ["a4 = 0x0807060504030201"])
+ self.match("register read x15", ["a5 = 0x0807060504030201"])
+ self.match("register read x16", ["a6 = 0x0807060504030201"])
+ self.match("register read x17", ["a7 = 0x0807060504030201"])
+ self.match("register read x18", ["s2 = 0x0807060504030201"])
+ self.match("register read x19", ["s3 = 0x0807060504030201"])
+ self.match("register read x20", ["s4 = 0x0807060504030201"])
+ self.match("register read x21", ["s5 = 0x0807060504030201"])
+ self.match("register read x22", ["s6 = 0x0807060504030201"])
+ self.match("register read x23", ["s7 = 0x0807060504030201"])
+ self.match("register read x24", ["s8 = 0x0807060504030201"])
+ self.match("register read x25", ["s9 = 0x0807060504030201"])
+ self.match("register read x26", ["s10 = 0x0807060504030201"])
+ self.match("register read x27", ["s11 = 0x0807060504030201"])
+ self.match("register read x28", ["t3 = 0x0807060504030201"])
+ self.match("register read x29", ["t4 = 0x0807060504030201"])
+ self.match("register read x30", ["t5 = 0x0807060504030201"])
+ self.match("register read x31", ["t6 = 0x0807060504030201"])
+
+
@skipIfXmlSupportMissing
@skipIfRemote
@skipIfLLVMTargetMissing("X86")
>From be1c2a0b1b2014b66fe0f4418230395a25016cc8 Mon Sep 17 00:00:00 2001
From: Kevin Per <kevin....@protonmail.com>
Date: Tue, 28 Jan 2025 16:28:52 +0000
Subject: [PATCH 3/3] Extended tests to check the aliases
---
.../postmortem/elf-core/TestLinuxCore.py | 145 ++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 376d6492d83b60..4c3391565277a3 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -704,39 +704,105 @@ def test_riscv64_regs_gpr_fpr(self):
process = target.LoadCore("linux-riscv64.gpr_fpr.core")
values = {}
+ alias = {}
values["pc"] = "0x000000000001016e"
+
values["ra"] = "0x00000000000101a4"
+ alias["x1"] = "ra"
+
values["sp"] = "0x0000003fffc1d2d0"
+ alias["x2"] = "sp"
+
values["gp"] = "0x0000002ae6eccf50"
+ alias["x3"] = "gp"
+
values["tp"] = "0x0000003ff3cb5400"
+ alias["x4"] = "tp"
+
values["t0"] = "0x7f7f7f7fffffffff"
+ alias["x5"] = "t0"
+
values["t1"] = "0x0000002ae6eb9b1c"
+ alias["x6"] = "t1"
+
values["t2"] = "0xffffffffffffffff"
+ alias["x7"] = "t2"
+
values["fp"] = "0x0000003fffc1d300"
+ alias["x8"] = "fp"
+
values["s1"] = "0x0000002ae6eced98"
+ alias["x9"] = "s1"
+
values["a0"] = "0x0"
+ alias["x10"] = "a0"
+
values["a1"] = "0x0000000000010144"
+ alias["x11"] = "a1"
+
values["a2"] = "0x0000002ae6ecedb0"
+ alias["x12"] = "a2"
+
values["a3"] = "0xafdbdbff81cf7f81"
+ alias["x13"] = "a3"
+
values["a4"] = "0x00000000000101e4"
+ alias["x14"] = "a4"
+
values["a5"] = "0x0"
+ alias["x15"] = "a5"
+
values["a6"] = "0x2f5b5a40014e0001"
+ alias["x16"] = "a6"
+
values["a7"] = "0x00000000000000dd"
+ alias["x17"] = "a7"
+
values["s2"] = "0x0000002ae6ec8860"
+ alias["x18"] = "s2"
+
values["s3"] = "0x0000002ae6ecedb0"
+ alias["x19"] = "s3"
+
values["s4"] = "0x0000003fff886c18"
+ alias["x20"] = "s4"
+
values["s5"] = "0x0000002ae6eceb78"
+ alias["x21"] = "s5"
+
values["s6"] = "0x0000002ae6ec8860"
+ alias["x22"] = "s6"
+
values["s7"] = "0x0000002ae6ec8860"
+ alias["x23"] = "s7"
+
values["s8"] = "0x0"
+ alias["x24"] = "s8"
+
values["s9"] = "0x000000000000000f"
+ alias["x25"] = "s9"
+
values["s10"] = "0x0000002ae6ecc8d0"
+ alias["x26"] = "s10"
+
values["s11"] = "0x0000000000000008"
+ alias["x27"] = "s11"
+
values["t3"] = "0x0000003ff3be3728"
+ alias["x28"] = "t3"
+
values["t4"] = "0x0"
+ alias["x29"] = "t4"
+
values["t5"] = "0x0000000000000002"
+ alias["x30"] = "t5"
+
values["t6"] = "0x0000002ae6ed08b9"
+ alias["x31"] = "t6"
+
values["zero"] = "0x0"
+ alias["x0"] = "zero"
+
values["fa5"] = "0xffffffff423c0000"
values["fcsr"] = "0x00000000"
@@ -788,6 +854,13 @@ def test_riscv64_regs_gpr_fpr(self):
substrs=["{} = {}".format(regname, fpr_value)],
)
+ for aliasname, regname in alias.items():
+ value = values[regname]
+ self.expect(
+ "register read {}".format(aliasname),
+ substrs=["{} = {}".format(regname, value)],
+ )
+
self.expect("register read --all")
@skipIfLLVMTargetMissing("RISCV")
@@ -798,39 +871,104 @@ def test_riscv64_regs_gpr_only(self):
process = target.LoadCore("linux-riscv64.gpr_only.core")
values = {}
+ alias = {}
values["pc"] = "0x0000000000010164"
+
values["ra"] = "0x0000000000010194"
+ alias["x1"] = "ra"
+
values["sp"] = "0x00fffffff4d5fcc0"
+ alias["x2"] = "sp"
+
values["gp"] = "0x0000000000157678"
+ alias["x3"] = "gp"
+
values["tp"] = "0x00ffffff99c43400"
+ alias["x4"] = "tp"
+
values["t0"] = "0x00ffffff99c6b260"
+ alias["x5"] = "t0"
+
values["t1"] = "0x00ffffff99b7bd54"
+ alias["x6"] = "t1"
+
values["t2"] = "0x0000000003f0b27f"
+ alias["x7"] = "t2"
+
values["fp"] = "0x00fffffff4d5fcf0"
+ alias["x8"] = "fp"
+
values["s1"] = "0x0000000000000003"
+ alias["x9"] = "s1"
+
values["a0"] = "0x0"
+ alias["x10"] = "a0"
+
values["a1"] = "0x0000000000010144"
+ alias["x11"] = "a1"
+
values["a2"] = "0x0000000000176460"
+ alias["x12"] = "a2"
+
values["a3"] = "0x000000000015ee38"
+ alias["x13"] = "a3"
+
values["a4"] = "0x00000000423c0000"
+ alias["x14"] = "a4"
+
values["a5"] = "0x0"
+ alias["x15"] = "a5"
+
values["a6"] = "0x0"
+ alias["x16"] = "a6"
+
values["a7"] = "0x00000000000000dd"
+ alias["x17"] = "a7"
+
values["s2"] = "0x0"
+ alias["x18"] = "s2"
+
values["s3"] = "0x000000000014ddf8"
+ alias["x19"] = "s3"
+
values["s4"] = "0x000000000003651c"
+ alias["x20"] = "s4"
+
values["s5"] = "0x00fffffffccd8d28"
+ alias["x21"] = "s5"
+
values["s6"] = "0x000000000014ddf8"
+ alias["x22"] = "s6"
+
values["s7"] = "0x00ffffff99c69d48"
+ alias["x23"] = "s7"
+
values["s8"] = "0x00ffffff99c6a008"
+ alias["x24"] = "s8"
+
values["s9"] = "0x0"
+ alias["x25"] = "s9"
+
values["s10"] = "0x0"
+ alias["x26"] = "s10"
+
values["s11"] = "0x0"
+ alias["x27"] = "s11"
+
values["t3"] = "0x00ffffff99c42000"
+ alias["x28"] = "t3"
+
values["t4"] = "0x00ffffff99af8e20"
+ alias["x29"] = "t4"
+
values["t5"] = "0x0000000000000005"
+ alias["x30"] = "t5"
+
values["t6"] = "0x44760bdd8d5f6381"
+ alias["x31"] = "t6"
+
values["zero"] = "0x0"
+ alias["x0"] = "zero"
for regname, value in values.items():
self.expect(
@@ -838,6 +976,13 @@ def test_riscv64_regs_gpr_only(self):
substrs=["{} = {}".format(regname, value)],
)
+ for aliasname, regname in alias.items():
+ value = values[regname]
+ self.expect(
+ "register read {}".format(aliasname),
+ substrs=["{} = {}".format(regname, value)],
+ )
+
# Check that LLDB does not try to read other registers from core file
self.expect(
"register read --all",
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