On Fri, Dec 11, 2015 at 07:30:29PM -0800, Haren Myneni wrote:
> NX842 coprocessor sets 3rd bit in CR register with XER[S0] which is
> nothing to do with NX request. On powerpc, XER[S0] will be set if
> overflow in FPU and stays until another floating point operation is
> executed. Since this bit can be set with other valuable return status,
> ignore this XER[S0] value.
XER[SO] is the *integer* summary overflow bit. It is set by OE=1
instructions ("addo" and the like), and can only be cleared explicitly
(using "mtxer").
The floating point overflow bit is FPSCR[OX].
> + /*
> + * NX842 coprocessor sets 3rd bit in CR register with XER[S0].
> + * Setting XER[S0] happens if overflow in FPU and stays until
> + * other floating operation is executed. XER[S0] value is nothing
> + * to NX and no use to user. Since this bit can be set with other
> + * return values, ignore this error.
> + */
> + if (ret & ICSWX_XERS0)
> + ret &= ~ICSWX_XERS0;
You can just always clear it, there is no need to check if it is set first.
Segher
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/linuxppc-dev
