On Fri, 2015-10-02 at 20:07 +1000, Alexey Kardashevskiy wrote: > On 08/19/2015 12:01 PM, Wei Yang wrote: > > In original design, it tries to group VFs to enable more number of VFs in > > the > > system, when VF BAR is bigger than 64MB. This design has a flaw in which one > > error on a VF will interfere other VFs in the same group. > > > > This patch series change this design by using M64 BAR in Single PE mode to > > cover only one VF BAR. By doing so, it gives absolute isolation between VFs. > > > > Wei Yang (6): > > powerpc/powernv: don't enable SRIOV when VF BAR has non > > 64bit-prefetchable BAR > > powerpc/powernv: simplify the calculation of iov resource alignment > > powerpc/powernv: use one M64 BAR in Single PE mode for one VF BAR > > powerpc/powernv: replace the hard coded boundary with gate > > powerpc/powernv: boundary the total VF BAR size instead of the > > individual one > > powerpc/powernv: allocate sparse PE# when using M64 BAR in Single PE > > mode > > > > arch/powerpc/include/asm/pci-bridge.h | 7 +- > > arch/powerpc/platforms/powernv/pci-ioda.c | 328 > > +++++++++++++++-------------- > > 2 files changed, 175 insertions(+), 160 deletions(-) > > I have posted few comments but in general the patchset makes things simpler > by removing a compound PE and does not seem to make things worse so: > > Acked-by: Alexey Kardashevskiy <a...@ozlabs.ru>
Thanks for reviewing it. I'll wait for a v5 that incorporates your comments. cheers _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
