Hi Boqun,
On Sun, Sep 20, 2015 at 09:23:03AM +0100, Boqun Feng wrote:
> On Sat, Sep 19, 2015 at 11:33:10PM +0800, Boqun Feng wrote:
> > On Fri, Sep 18, 2015 at 05:59:02PM +0100, Will Deacon wrote:
> > > On Wed, Sep 16, 2015 at 04:49:31PM +0100, Boqun Feng wrote:
> > > > On powerpc, we don't need a general memory barrier to achieve acquire
> > > > and
> > > > release semantics, so __atomic_op_{acquire,release} can be implemented
> > > > using "lwsync" and "isync".
> > >
> > > I'm assuming isync+ctrl isn't transitive, so we need to get to the bottom
> >
> > Actually the transitivity is still guaranteed here, I think ;-)
The litmus test I'm thinking of is:
{
0:r2=x;
1:r2=x; 1:r5=z;
2:r2=z; 2:r4=x;
}
P0 | P1 | P2 ;
li r1,1 | lwz r1,0(r2) | lwz r1,0(r2) ;
stw r1,0(r2) | cmpw r1,r1 | cmpw r1,r1 ;
| beq LC00 | beq LC01 ;
| LC00: | LC01: ;
| isync | isync ;
| li r4,1 | lwz r3,0(r4) ;
| stw r4,0(r5) | ;
exists
(1:r1=1 /\ 2:r1=1 /\ 2:r3=0)
Which appears to be allowed. I don't think you need to worry about backwards
branches for the ctrl+isync construction (none of the current example do,
afaict).
Anyway, all the problematic cases seem to arise when we start mixing
ACQUIRE/RELEASE accesses with relaxed accesses (i.e. where an access from
one group reads from an access in the other group). It would be simplest
to say that this doesn't provide any transitivity guarantees, and that
an ACQUIRE must always read from a RELEASE if transitivity is required.
Will
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