On Fri, Jul 17, 2015 at 10:14:41AM +1000, Gavin Shan wrote: >When the VF BAR size is equal to 128MB or bigger than that, the IOV BAR >is extended to cover number of maximal VFs supported by the PF, not 256. >Also, one PHB's M64 BAR is picked to cover VF BARs for 4 continous VFs, >but the PHB's M64 BAR is configured as being owned by single PE. Eventually, >those 4 VFs have 4 separate PEs from the perspective of PCI config or DMA, >but single shared PE from MMIO's perspective. Once we have compound PE, all >those 4 VFs included in the compound PE can't be passed to separate guests >with VFIO infrastructure. > >The above gate (128MB) was choosen based on the assumption: one IOV BAR can >consume 1/4 of PHB's M64 window, which is 16GB. However, it can consume as >much as half of that (32GB) when the PF seats behind the root port. >Accordingly, >the gate can be doubled to be 256MB in order to avoid compound PE as we can. > >
Please ignore those two patches as Richard already sent one patch fixing it in better way. Sorry for the noise! Thanks, Gavin >Gavin Shan (2): > powerpc/powernv: Fix alignment for IOV BAR > powerpc/powernv: Double VF BAR size for compound PE > > arch/powerpc/platforms/powernv/pci-ioda.c | 56 +++++++++++++++++++++++++------ > 1 file changed, 45 insertions(+), 11 deletions(-) > >-- >2.1.0 > _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
