From: Xie Xiaobo <x....@freescale.com> A ioport setting was needed when used the QE uart function on TWR-P1025. Added a conditional definition to avoid missing this setting when the QE-uart driver was bulit to a module.
Signed-off-by: Xie Xiaobo <x....@freescale.com> Change-Id: I95b40c760335ce5fa7a27a94287dbef28219b5fa Reviewed-on: http://git.am.freescale.net:8181/6643 Tested-by: Review Code-CDREVIEW <cdrev...@freescale.com> Reviewed-by: Yang Li <le...@freescale.com> Reviewed-by: Thomas Trefny <tom.tre...@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/12045 Reviewed-by: Jose Rivera <german.riv...@freescale.com> --- arch/powerpc/platforms/85xx/twr_p102x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c index 1eadb6d..069e19b 100644 --- a/arch/powerpc/platforms/85xx/twr_p102x.c +++ b/arch/powerpc/platforms/85xx/twr_p102x.c @@ -101,7 +101,7 @@ static void __init twr_p1025_setup_arch(void) MPC85xx_PMUXCR_QE(12)); iounmap(guts); -#if defined(CONFIG_SERIAL_QE) +#if defined(CONFIG_SERIAL_QE) || defined(CONFIG_SERIAL_QE_MODULE) /* On P1025TWR board, the UCC7 acted as UART port. * However, The UCC7's CTS pin is low level in default, * it will impact the transmission in full duplex -- 2.1.0.27.g96db324 _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
