On Fri, 2014-12-05 at 10:01 +0530, Mahesh J Salgaonkar wrote:
> From: Mahesh Salgaonkar <mah...@linux.vnet.ibm.com>
>
> The existing MCE code calls flush_tlb hook with IS=0 (single page) resulting
> partial invalidation of TLBs which is not right. This patch fixes that
> by passing IS=0xc00 to invalidate whole TLB for successful recovery from
> TLB and ERAT errors.
What does "TLBIEL_INVAL_SET" means in that context ? Invalidating a set
isn't the same thing as invalidating the TLB ... and that makes no sense
without passing the page address or set # as an argument anyway
I still don't understand your flush_tlb() interface... it's arguments
don't make sense
Ben.
> Signed-off-by: Mahesh Salgaonkar <mah...@linux.vnet.ibm.com>
> ---
> Hi Michael,
> This MCE fix patch is for stable.
>
> arch/powerpc/kernel/mce_power.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
> index aa9aff3..b6f123a 100644
> --- a/arch/powerpc/kernel/mce_power.c
> +++ b/arch/powerpc/kernel/mce_power.c
> @@ -79,7 +79,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t
> slb_error_bits)
> }
> if (dsisr & P7_DSISR_MC_TLB_MULTIHIT_MFTLB) {
> if (cur_cpu_spec && cur_cpu_spec->flush_tlb)
> - cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
> + cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);
> /* reset error bits */
> dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
> }
> @@ -110,7 +110,7 @@ static long mce_handle_common_ierror(uint64_t srr1)
> break;
> case P7_SRR1_MC_IFETCH_TLB_MULTIHIT:
> if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
> - cur_cpu_spec->flush_tlb(TLBIEL_INVAL_PAGE);
> + cur_cpu_spec->flush_tlb(TLBIEL_INVAL_SET);
> handled = 1;
> }
> break;
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