On 8/22/2014 11:21 PM, Scott Wood wrote:
On Fri, 2014-08-22 at 20:07 +0530, Prabhakar Kushwaha wrote:
Sorry Scott for late reply,
Please find my reply in-lined
On 8/21/2014 4:51 AM, Scott Wood wrote:
On Wed, 2014-08-20 at 09:05 +0530, Prabhakar Kushwaha wrote:
On 8/20/2014 5:38 AM, Scott Wood wrote:
On Fri, 2014-08-15 at 16:07 -0500, Aaron Sierra wrote:
Freescale's QorIQ T Series processors support 8 IFC chip selects
within a memory map backward compatible with previous P Series
processors which supported only 4 chip selects.
Signed-off-by: Aaron Sierra <asie...@xes-inc.com>
---
include/linux/fsl_ifc.h | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/linux/fsl_ifc.h b/include/linux/fsl_ifc.h
index 84d60cb..62762ff 100644
--- a/include/linux/fsl_ifc.h
+++ b/include/linux/fsl_ifc.h
@@ -29,7 +29,7 @@
#include <linux/of_platform.h>
#include <linux/interrupt.h>
-#define FSL_IFC_BANK_COUNT 4
+#define FSL_IFC_BANK_COUNT 8
First please modify fsl_ifc_nand.c to limit itself to the number of
banks it dynamically determines are present based on the IFC version.
Number of available bank/chip select are defined by SoC and it is
independent of SoC.
Do you mean defined by the SoC and independent of the IFC version?
IFC v 1.0.0 supports 4 Chip Select.
IFC v 1.1.0 onwards, IFC supports 8 chip select.
But SoC finally defines number of chip select coming out of SoC. Like
LS1021A with IFC ver 1.4.0 have only 7 Chip Select.
What matters here is whether the registers are implemented, not whether
a chip select is pinned out -- so use the IFC version.
I checked with IFC IP team " There is no side-effect of reading CS-8
register if only 7 CS exposed by SoC"
IFC version can be used.
Regards,
Prabhakar
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