Currently, all MMIO resources, including 64-bits MMIO resources are hooked
to PHB 32-bits MMIO BAR, which has limited space. If there're PCI devices
with large 64-bits MMIO BAR (could reach 1GB), we're running out of MMIO
resources (as well as PE numbers) quickly. The patchset reuses the M32
infrastructure to support M64:
* The last M64 BAR covers all M64 aperatus and that's shared by all PEs.
* Reuse ppc_md.pcibios_window_alignment() to affect resource assignment
in PCI core so that we can get well segmented 64-bits window of PCI
bridges.
* One PCI bus might require multiple discrete M64 segment. We invent
if we're going to unfreeze any one in the group.
The patchset requires corresponding changes from firmware. And we don't
support M64 for P7 yet. That's something to do in future.
Gavin Shan (5):
powerpc/powernv: Allows to freeze PE
powerpc/powernv: Split ioda_eeh_get_state()
powerpc/powernv: handle compound PE
powerpc/powernv: Handle compound PE for EEH
powerpc/powernv: Handle compound PE in config accessors
Guo Chao (1):
powerpc/powernv: Enable M64 aperatus for PHB3
arch/powerpc/include/asm/opal.h | 17 +-
arch/powerpc/platforms/powernv/eeh-ioda.c | 293 ++++++++++-------
arch/powerpc/platforms/powernv/opal-wrappers.S | 2 +-
arch/powerpc/platforms/powernv/pci-ioda.c | 432 ++++++++++++++++++++++++-
arch/powerpc/platforms/powernv/pci.c | 87 +++--
arch/powerpc/platforms/powernv/pci.h | 23 ++
6 files changed, 685 insertions(+), 169 deletions(-)
--
1.8.3.1
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