On Feb 7, 2014, at 3:02 AM, Torsten Duwe <d...@lst.de> wrote: > On Thu, Feb 06, 2014 at 02:19:52PM -0600, Scott Wood wrote: >> On Thu, 2014-02-06 at 18:37 +0100, Torsten Duwe wrote: >>> On Thu, Feb 06, 2014 at 05:38:37PM +0100, Peter Zijlstra wrote: >> >>>> Can you pair lwarx with sthcx ? I couldn't immediately find the answer >>>> in the PowerISA doc. If so I think you can do better by being able to >>>> atomically load both tickets but only storing the head without affecting >>>> the tail. > > Can I simply write the half word, without a reservation, or will the HW caches > mess up the other half? Will it ruin the cache coherency on some > (sub)architectures?
The coherency should be fine, I just can’t remember if you’ll lose the reservation by doing this. >> Plus, sthcx doesn't exist on all PPC chips. > > Which ones are lacking it? Do all have at least a simple 16-bit store? Everything implements a simple 16-bit store, just not everything implements the store conditional of 16-bit data. - k _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
