> -----Original Message----- > From: Kumar Gala [mailto:ga...@kernel.crashing.org] > Sent: Tuesday, September 24, 2013 9:19 PM > To: Bhushan Bharat-R65777 > Cc: Wang Dongsheng-B40534; Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org > Subject: Re: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 > define > > > On Sep 24, 2013, at 6:21 AM, Bhushan Bharat-R65777 wrote: > > > > > > >> -----Original Message----- > >> From: Linuxppc-dev [mailto:linuxppc-dev- > >> bounces+bharat.bhushan=freescale....@lists.ozlabs.org] On Behalf Of > >> bounces+Dongsheng > >> Wang > >> Sent: Tuesday, September 24, 2013 2:58 PM > >> To: Wood Scott-B07421 > >> Cc: linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-B40534 > >> Subject: [PATCH v4 1/4] powerpc/fsl: add E6500 PVR and SPRN_PWRMGTCR0 > >> define > >> > >> From: Wang Dongsheng <dongsheng.w...@freescale.com> > >> > >> E6500 PVR and SPRN_PWRMGTCR0 will be used in subsequent pw20/altivec > >> idle patches. > >> > >> Signed-off-by: Wang Dongsheng <dongsheng.w...@freescale.com> > >> --- > >> *v3: > >> Add bit definitions for PWRMGTCR0. > >> > >> arch/powerpc/include/asm/reg.h | 2 ++ > >> arch/powerpc/include/asm/reg_booke.h | 9 +++++++++ > >> 2 files changed, 11 insertions(+) > >> > >> diff --git a/arch/powerpc/include/asm/reg.h > >> b/arch/powerpc/include/asm/reg.h index 64264bf..d4160ca 100644 > >> --- a/arch/powerpc/include/asm/reg.h > >> +++ b/arch/powerpc/include/asm/reg.h > >> @@ -1053,6 +1053,8 @@ > >> #define PVR_8560 0x80200000 > >> #define PVR_VER_E500V1 0x8020 > >> #define PVR_VER_E500V2 0x8021 > >> +#define PVR_VER_E6500 0x8040 > >> + > >> /* > >> * For the 8xx processors, all of them report the same PVR family for > >> * the PowerPC core. The various versions of these processors must be > >> diff -- git a/arch/powerpc/include/asm/reg_booke.h > >> b/arch/powerpc/include/asm/reg_booke.h > >> index ed8f836..4a6457e 100644 > >> --- a/arch/powerpc/include/asm/reg_booke.h > >> +++ b/arch/powerpc/include/asm/reg_booke.h > >> @@ -170,6 +170,7 @@ > >> #define SPRN_L2CSR1 0x3FA /* L2 Data Cache Control and Status > >> Register 1 > >> */ > >> #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ > >> #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ > >> +#define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 > >> */ > > > > Is this generic for booke or e6500 specific? I can't see this register > > either > in ISA and EREF. > > Also I can see SPRN_ICCR also with same SPRN, how that is possible? > > Its possibly because the register maybe in implementation specific region. > I'm > guessing ICCR is a 40x specific register.
Kumar, this seems to create confusion? Although I do not like so many header files but still I think we can have reg_4xx.h, reg_fsl_booke.h etc for implementation specific definitions. -Bharat > > - k > _______________________________________________ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
