On Tue, May 14, 2013 at 04:05:56PM +0800, Dongsheng Wang wrote:
> This problem belongs to the core synchronization issues.
> The cpu1 already updated spin_table values, but bootcore cannot get
> this value in time.
>
> After bootcpu hibiernation restore the pages. we are now running
> with the kernel data of the old kernel fully restored. if we reset
> the non-bootcpus that will be reset cache(tlb), the non-bootcpus
> will get new address(map virtual and physical address spaces).
> but bootcpu tlb cache still use boot kernel data, so we need to
> invalidate the bootcpu tlb cache make it to get new main memory data.
>
> log:
> Enabling non-boot CPUs ...
> smp_85xx_kick_cpu: timeout waiting for core 1 to reset
> smp: failed starting cpu 1 (rc -2)
> Error taking CPU1 up: -2
>
> Signed-off-by: Wang Dongsheng <dongsheng.w...@freescale.com>
> Reviewed-by: Anton Vorontsov <an...@enomsg.org>
>
>
> diff --git a/arch/powerpc/kernel/swsusp_booke.S
> b/arch/powerpc/kernel/swsusp_booke.S
> index 11a3930..9503249 100644
> --- a/arch/powerpc/kernel/swsusp_booke.S
> +++ b/arch/powerpc/kernel/swsusp_booke.S
> @@ -141,6 +141,19 @@ _GLOBAL(swsusp_arch_resume)
> lis r11,swsusp_save_area@h
> ori r11,r11,swsusp_save_area@l
>
> + /*
> + * The boot core get a virtual address, when the boot process,
> + * the virtual address corresponds to a physical address. After
> + * hibernation resume memory snapshots, The corresponding
> + * relationship between the virtual memory and physical memory
> + * might change again. We need to get a new page table. So we
> + * need to invalidate TLB after resume pages.
> + *
> + * Invalidations TLB Using tlbilx/tlbivax/MMUCSR0.
> + * tlbilx used here.
> + */
> + bl _tlbil_all
Applied with the code comment changed to:
/*
* Mappings from virtual addresses to physical addresses may be
* different than they were prior to restoring hibernation state.
* Invalidate the TLB so that the boot CPU is using the new
* mappings.
*/
-Scott
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